參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 145/153頁
文件大小： 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
91
30A09
[0:7]
B1_ERR_CNT
00
Error counter that increments when a section
B1 error is detected on a link. The link is
selected using ERRCNT_CHSEL. This counter
is cleared on read.
Both
30A0A
[0:7]
CELL_BIP_ERR_CNT
00
Cell BIP Error Counter, Error counter that incre-
ments when a Cell BIP error is detected on a
link. The link being monitored is selected using
ERRCNT_CHSEL. This counter is cleared on
read.
Cell
30A0B
[0:2]
RSVD
00
Reserved
[3]
CELL_DRP_B2
Cell Drop, CELL_DRP_B2 = 1 indicates that a
cell has been dropped from the link group BC
and BD
Cell
[4]
RSVD
Reserved
—
[5]
CELL_DRP_A2
Cell Drop, CELL_DRP_A2 = 1 indicates that a
cell has been dropped from the link group AC
and AD
Cell
[6:7]
RSVD
Reserved
—
30A0C
[0:1]
RSVD
00
Reserved
[2]
SYNC2_B2_OOS
SYNC2_B2_OOS = 1 indicates that channels
cannot be aligned within the links BC and BD in
SONET mode
SONET
[3:4]
RSVD
Reserved
—
[5]
SYNC2_A2_OOS
SYNC2_A2_OOS = 1 indicates that channels
cannot be aligned within the AC and AD links in
SONET mode
SONET
[6:7]
SYNC2_A1_OOS
Reserved
—
30A0D
[0:1]
RSVD
00
Reserved
—
[2]
SYNC2_B2_OVFL
SYNC2_B2_OVFL = 1 indicates that the align-
ment FIFO(s) in the links BC and BD are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[3:4]
RSVD
Reserved
—
[5]
SYNC2_A2_OVFL
SYNC2_A2_OVFL = 1 indicates that the align-
ment FIFO(s) in the links AC and AD are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[6:7]
RSVD
Reserved
—
30A0E
[0:2]
RSVD
00
Reserved
[3]
BDL_ALIGN_ERR_B2
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs BC and BD
Cell
[4]
RSVD
Reserved
—
[5]
BDL_ALIGN_ERR_A2
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs AC and AD
Cell
[6:7]
RSVD
Reserved
—
Table 28. Common Control Register Descriptions – ORSO42G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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