參數(shù)資料
型號(hào)： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 71/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
24
Figure 10. Bit and Byte Alignment for DEMUX Block
SONET Mode Operation – Detailed Description
The following sections describe the data processing performed in the SONET logic blocks. The basic data ows in
the SONET Mode are shown in Figure 11. At a top level, the descriptions are separated into processing in the
transmit path (FPGA to serial link) and processing in the receive path (serial link to FPGA). In general, the descrip-
tions in the next sections are written to describe SONET mode operation, although some of the “SONET logic
blocks” are also used in cell mode operation. The various processing options are selected by setting bits in control
registers and status information is written to status registers. Both types of registers can be written and/or read
from the System Bus. Memory maps and descriptions for the registers are given in Table 21 through Table 36.
Figure 11. Basic Data Flows - SONET Mode
In the SONET mode, the transmit block receives 32-bit wide data from the FPGA (DINxx) on each of its channels
along with a frame pulse (DINxx_FP) per channel and a transmit clock (TSYCLKxx). Typically this will represent a
STS-48 stream on each link. The data are rst passed through a TOH block which will generate all the timing
pulses that are required to isolate individual overhead bytes (e.g., A1, A2, B1, D1-D3, etc.). The timing pulse gener-
Time
W
O
R
D
3
W
O
R
D
2
W
O
R
D
1
W
O
R
D
0
8:32
DEMUX
W
0
W
1
W
2
W
3
Bit and Byte alignment of
LDOUT[0:7] through the
8:32 DEMUX block
to the 32-bit 77MHz data bus
7
0
7
0
31
0
Pseudo-
SONET
Processing
User
I/O
Receive (RX) Path
Transmit (TX) Path
Cell
Processing
Pseudo-
SONET
Processing
Configurable
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
Configurable
as
four
or
eight
data
channels
organized
in
two
blocks
相關(guān)PDF資料
PDF描述
ORSO42G5-3BMN484C IC TRANCEIVERS FPSC 680FPGAM
ORT82G5-1FN680I IC TRANCEIVERS FPSC 680FPBGA
ORT82G5-2FN680I IC TRANCEIVERS FPSC 680FPBGA
VI-J4H-IW-F4 CONVERTER MOD DC/DC 52V 100W
VI-J4H-IW-F3 CONVERTER MOD DC/DC 52V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*