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| 型號(hào)： | ORSO42G5-2BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 129/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
77
The ORSO42G5 and ORSO82G5 core registers do not check for parity on a write operation. On a read operation,
no parity is generated, and a “0” is passed back to the initiating bus master interface on the parity signal line.
Types of Registers
The registers in ORSO42G5 and ORSO82G5 are 8-bit memory locations which, in general, can be classied into
several types:
General Core Status Registers
Read-only registers to convey the status information of various operations within the FPSC core. An example is the
state of the LKI-xx receive PLL lock indicator outside the SERDES.
Alarm Status and Mask Registers
The alarm status registers are enabled or masked by the corresponding alarm enable registers. An example of
such an alarm is the Out-Of-Frame (OOF) bit OOF_xx which is enabled by the corresponding alarm enable bit
OOF_ENxx (xx indicates one of the SERDES channels). (The OOF and BIP error alarms are also available as sig-
nals across the core-FPGA boundary for each channel.) All the alarms for a given channel will be read into a single
status bit (ALARM_STATUS_[AA-BD]). In addition, an event on any of these alarm status bits will generate an inter-
rupt to the FPSC slave of the interrupt cause register on the system bus interface (see technical note TN1017). All
alarm and status registers are clear on read.
Control Registers
Read-write registers to setup the control inputs that dene the operation of the FPSC core. The SERDES block
within the ORSO42G5 and ORSO82G5 core has a set of status and control registers for it’s operation. There is
another group of status and control registers which are implemented outside the SERDES, which are related to the
SERDES and other functional blocks in the FPSC core. They will be described in detail here.
Each SERDES has four independent channels, which are named A, B, C or D. Using this nomenclature, the SER-
DES A channels are named as AA, AB, AC and AD, while SERDES B channels will be BA, BB,BC and BD. The
register address allocation for the ORSO82G5 is shown in Table 20. Detailed descriptions of all of the register bits
Table 20. Memory Space Allocation in the FPSC Core
Address (Hex)
Description
3000x
Channel A in SERDES A block, internal registers (not available in the ORSO42G5)
3001x
Channel B in SERDES A block, internal registers (not available in the ORSO42G5)
3002x
Channel C in SERDES A block, internal registers
3003x
Channel D in SERDES A block, internal registers
3010x
Channel A in SERDES B block, internal registers (not available in the ORSO42G5)
3011x
Channel B in SERDES B block, internal registers (not available in the ORSO42G5)
3012x
Channel C in SERDES B block, internal registers
3013x
Channel D in SERDES B block, internal registers
3080x
Channel AA registers outside the SERDES (not available in the ORSO42G5)
3081x
Channel AB registers outside the SERDES (not available in the ORSO42G5)
3082x
Channel AC registers outside the SERDES
3083x
Channel AD registers outside the SERDES
3090x
Channel BA registers outside the SERDES (not available in the ORSO42G5)
3091x
Channel BB registers outside the SERDES (not available in the ORSO42G5)
3092x
Channel BC registers outside the SERDES
3093x
Channel BD registers outside the SERDES
30Axx
All Channels registers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ORSO42G5-3BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
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