參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 67/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
20
of differential 0.6 to 2.7 Gbit/s links. At the FPGA/Embedded Core interface, the data are transferred across 32-bit
buses. The SERDES blocks themselves are organized as two blocks. Each of the data paths is identied with a
block and channel identier (i.e., AC, AD, BC, BD or AA,...,BD).
Each channel has a 32-bit TX bus, 32-bit RX bus, a recovered clock, a transmit clock input and a transmit start sig-
nal.
Figure 5. Basic Data Flows - SERDES Only Mode
Figure 6 shows a block diagram of a single channel of the SERDES block. The transmitter section accepts either
scrambled or un-scrambled data at the parallel input port. It also accepts the low-speed reference clock at the REF-
CLK input and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data are avail-
able at the differential CML output terminated in 86 Ω to drive either an optical transmitter, coaxial media or a circuit
board/backplane.
Figure 6. SERDES Functional Block Diagram for One Channel
Transmit (TX) Path
Receive (RX) Path
Cell
Processing
Pseudo-
SONET
Processing
Configurable
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
Configurable
as
four
or
eight
data
channels
organized
in
two
SERDES
blocks
User
I/O
TX PLL
SERIAL
Output Control
HDOUT P/N
XCK311
MUX
LDIN[7:0]
HAMP
PE
Data
Rate
TXHR
RX PLL
REFCLK P/N
RWCK
LDOUT[7:0]
PARALLEL
RBC
RXHR
LCKREFN
HDIN P/N
NELB
FELB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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