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| 型號(hào)： | ORSO42G5-2BMN484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 93/153頁 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
44
SPE Generator
The SPE generator in the ORSO42G5 and ORSO82G5 is used to indicate the payload and overhead portions of a
SONET frame. It is present in the SONET data path only. The SPE generator generates row, column and STS
counters based on the frame pulse received from the (24 x 33) alignment FIFO or from the descrambler if align-
ment FIFOs are bypassed. It also retimes the 32-bit data in order to align it with the SPE indicator. The SPE gener-
ator will also detect negative or positive pointer justication (if justication is enabled) by looking at the ID bits in the
H1 and H2 bytes and adjust the SPE indicator for the STS-1 frame being justied as follows:
During positive pointer justication, the SPE will be low during H3 byte and the SPE byte following it.
During negative pointer justication, the SPE will be high during H3 byte.
During no justication, the SPE will be low during H3 byte.
This block only detects the incoming pointer bytes for SPE generation. This capability can be enabled by software
control. By default, the SPE generator will ignore any pointer justication. This block has no capability of any
pointer processing, pointer checking or pointer mover operation and ignores “new data” indications from the
SONET specication.
SONET Mode Receive Timing – ORSO42G5
This section contains timing diagrams for major interfaces of this block to the FPGA logic when SONET frames are
to be transferred.
When operating in SONET mode, the entire SONET frame is sent to the FPGA. In multi-channel alignment
mode(s), data from all channels within an alignment group are aligned to the A1A2 framing bytes.
Each SONET frame is 125μs. The frame starts with 36 clock cycles (77.76 MHz) of TOH followed by 1044 clock
cycles of SPE, followed by 36 clock cycles of TOH, 1044 cycles of SPE.
The DOUTxx_SPE signal indicates TOH or SPE in the data (low for TOH, high for SPE)
Twin pairs are AC, AD (group A2) and BC, BD (group B2)
Figure 32 shows the SONET twin alignment mode timing for the ORSO42G5. The frame pulse and SPE indicators
are show for each of the two channels (AC, AD) in twin alignment.
Figure 30. Receive Clocking Diagram for SONET Mode Twin Alignment in Block A – ORSO42G5
RSYSCLKA2
DOUTAC[31:0]
DOUTAC_FP
TT
T
S
SS
T
SSSS
S
...
1 cycle
36 cycles TOH
1
044 cycles SPE
36 cycles TOH
Start of Frame
125 μs
Data
T Represents TOH
S Represents SPE
DOUTxx-SPE is high for SPE, low for TOH
Clocks
RSYSCLKA2 is the read clock used for group A2
RSYSBLKB2 is the read clock used for group B2
36 cycles TOH
TT
T
S
SS
T
SSSS
S
Start of Frame
DOUTAC_SPE
DOUTAD[31:0]
DOUTAD_SPE
DOUTAD_FP
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PDF描述 |
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| ORSO42G5-3BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| ORT82G5-1FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| ORT82G5-2FN680I | IC TRANCEIVERS FPSC 680FPBGA |
| VI-J4H-IW-F4 | CONVERTER MOD DC/DC 52V 100W |
| VI-J4H-IW-F3 | CONVERTER MOD DC/DC 52V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORSO82G5 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
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