參數(shù)資料
型號: ORSO42G5-2BMN484C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 24/153頁
文件大?。?/td> 0K
描述: IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告: Product Discontinuation 01/Aug/2011
標準包裝: 60
系列: *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
12
Support for OC-48 and OC-192 (in block OC-48) formats.
SONET framing, scrambling and SONET Mode channel alignment.
Performance monitoring functions such as Bit Interleaved Parity (BIP-8) generation and checking and Out-Of-
Frame (OOF) and Remote Defect Indication (RDI-L) detection.
Cell Mode cell creation and extraction, idle cell insertion/deletion, destriping and striping functions.
Additionally, there are two independent memory blocks in the core. Each embedded RAM block has a capacity of
4K words by 36 bits.
The ORSO42G5 and ORSO82G5 embedded cores contain, respectively, four-channel and eight-channel clock and
data recovery macrocells and logical blocks performing functions such as SONET framing, scrambling/descram-
bling and cell processing. The channels each operate from 0.6 to 2.7 Gbps with per channel CDR functionality. The
CDR interface enables high-speed asynchronous serial data transfer between system devices. Devices can be on
the same PC-board, on separate boards connected across a backplane, or connected by cables. Figure 2 shows a
top level block diagram of the backplane driver logic in the embedded core (embedded RAM not shown).
Figure 2. Top Level Block Diagram ORSO42G5 and ORSO82G5 Embedded Cores
ORSO42G5 and ORSO82G5 Main Operating Modes - Overview
The ORSO42G5 and ORSO82G5 support four and eight 0.6 to 2.7 Gbps serial data channels respectively, which
can operate independently or can be combined together (aligned) to achieve higher bit rates. The mode of opera-
tion of the core is dened by a set of control registers, which can be written through the system bus interface. The
status of the core is stored in a set of status registers, which can be read through the system bus interface.
The serial data channels support OC-48 rates on each channel. The standard OC-48 rate, 2.488 Gbits, is used as
the nominal data rate for the technical discussions that follow. OC-192 is also supported but is transmitted and
received in block OC-48 links. The scrambled data stream conforms to the GR-255 specied polynomial sequence
of 1+x
6+x7.
There are three main operating modes in the ORSO42G5 and ORSO82G5 as described below:
SERDES only (bypass) mode
SONET mode
Cell mode
– Two-link sub-mode
– Eight-link sub-mode (ORSO82G5 only)
Transmit (TX) Path
Receive (RX) Path
Cell
Processing
Configurable
as
four
or
eight
data
channels
organized
in
two
blocks
User
Configurable
I/O
Psuedo-
SONET
Processing
ORCA 4E04
FPGA Logic
MUX/DEMUX
and
SERDES
相關(guān)PDF資料
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