參數(shù)資料
型號： ORSO42G5-2BMN484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 123/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPGAM
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
71
Toggle SOFT_RESET once all clocks have stabilized
– 30A06
01
– 30A06
00
Provide a rising edge on the DIXxx_START signal
2. SONET Mode Initialization – ORSO82G5
This sample initialization uses the alignment FIFO for 4 channel alignment and Auto_SOH mode
Set 4 Channel Alignment (per channel, all channels in block A)
– 30802, etc. 60
Set SERDES PLL to Lock to Data signal (per channel, all channels in block A)
– 30804, etc. 80
Set Auto_Soh Mode (per channel, all channels in block A)
– 30806, etc. 03
Set NO_TX_RDI_EXSEQ Global register (block A). This is required to stop cell mode blocks from sending RDI
due to no cells.
– 30A03
80
Toggle SOFT_RESET once all clocks have stabilized
– 30A06
01
– 30A06
00
3. SONET Alignment FIFO Resynchronization – ORSO82G5
If during operation a link goes OOF the alignment group will continue to run without the errored channel. To realign
this link with the rest of group once the OOF condition is cleared the group may need to be resynchronized. This
operation (for 4 channel alignment in block A) is shown below.
Toggle the FMPU_RESYNC4_4 register bit to reset the alignment FIFO group.
– 30A04
48
– 30A04
00
This sequence will stop trafc temporarily on all links in the alignment grouping.
4. Two-Link Cell Mode Initialization – ORSO82G5
This sample initialization uses 2-link cell mode on all links (A1, A2, B1, and B2). Auto_Bundle and Auto_Remove
are both used for these links. The GSWRST_[A:B] Rejoin method is used.
Set SERDES PLL to Lock to Data signal and Auto_TOH mode (per channel, all channels)
– 30804, etc. 82
Set Auto_Remove and Rejoin
– 30A03
1B
Set 2-link cell mode for all groups A1, A2, B1 and B2
– 30A05
1E
Toggle SOFT_RESET
– 30A06
01
– 30A06
00
Set the TX_CFG_DONE bit to indicate the transmitter is completely congured
– 30A07
01
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORSO82G5 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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