L
G
R
Core Timer
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
100
Core Timer
MOTOROLA
interrupt period of about 250ms seconds at a crystal frequency of
1 MHz. RTIF is a read-only status bit and is set when the output of the
chosen (1 of 4 selection) stage goes active. A CPU interrupt request
will be generated if RTIE is set. Reset clears RTIF.
TOFE – Timer Over Flow Enable
When this bit is set, a CPU interrupt request is generated when the
TOF bit is set. Reset clears this bit.
RTIE – Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
RTOF — Reset Timer Overflow Flag
This bit reads always as ‘0’. Writing a ‘1’ to this bit clears the timer
overflow flag (TOF). Writing a zero to this bit has no effect.
RRTIF — Reset Real Time Interrupt Flag
This bit reads always a ‘0’. Writing a ‘1’ to this bit clears the real time
interrupt flag (RTIF). Writing a zero to this bit has no effect.
RT1, RT0 – Real Time Interrupt Rate Select
These two bits select one of four taps from the real time interrupt
circuit.
Figure 8-1
shows the available interrupt rates with several f
op
values. Reset sets these RT0 and RT1, selecting the lowest periodic
rate and therefore the maximum time in which to alter these bits if
necessary. Care should be taken when altering RT0 and RT1 if the
time-out period is imminent or uncertain. If the selected tap is modified
during a cycle in which the counter is switching, an RTIF could be
missed or an additional one could be generated. To avoid problems,
the COP should be cleared before changing RTI taps.
Table 8-1. RTI Rates
RTI Rates at Bus Frequency f
OP
specified:
RT1:RT0
500 kHz
1.000 MHz
2.000 MHz
2.4576 MHz
RATIO
00
32.768ms
16.384ms
8.192ms
6.667ms
2
14
/f
op