L
G
R
CPU and Instruction Set
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
56
CPU and Instruction Set
MOTOROLA
ROR opr
RORA
RORX
ROR oprX
ROR ,X
Rotate Byte Right through Carry Bit
— —
¤
¤
¤
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
5
3
3
6
5
RSP
Reset Stack Pointer
SP
←
$00FF
— — — — —
INH
9C
2
RTI
Return from Interrupt
SP
←
(SP) + 1; Pull (CCR)
SP
←
(SP) + 1; Pull (A)
SP
←
(SP) + 1; Pull (X)
SP
←
(SP) + 1; Pull (PCH)
SP
←
(SP) + 1; Pull (PCL)
SP
←
(SP) + 1; Pull (PCH)
SP
←
(SP) + 1; Pull (PCL)
¤
¤
¤
¤
¤
INH
80
9
RTS
Return from Subroutine
— — — — —
INH
81
6
SBC #opr
SBC opr
SBC opr
SBC oprX
SBC oprX
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
A
←
(A) – (M) – (C)
— —
¤ ¤
¤
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SEC
Set Carry Bit
C
←
1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I
←
1
— 1 — — —
INH
9B
2
STA opr
STA opr
STA oprX
STA oprX
STA ,X
Store Accumulator in Memory
M
←
(A)
— —
¤
¤
—
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
dd
hh ll
ee ff
ff
4
5
6
5
4
STX opr
STX opr
STX oprX
STX oprX
STX ,X
Store Index Register In Memory
M
←
(X)
— —
¤
¤
—
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
dd
hh ll
ee ff
ff
4
5
6
5
4
SUB #opr
SUB opr
SUB opr
SUB oprX
SUB oprX
SUB ,X
Subtract Memory Byte from Accumulator
A
←
(A) – (M)
— —
¤
¤
¤
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SWI
Software Interrupt
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
— 1 — — —
INH
83
10
TAX
Transfer Accumulator to Index Register
X
←
(A)
— — — — —
INH
97
2
Table 3-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
H I N Z C
b0
b7
C