
L
G
R
Serial Peripheral Interface (SPI)
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
116
Serial Peripheral Interface (SPI)
MOTOROLA
Features include:
Full-duplex, 3-wire synchronous transfers
Master or slave operation
2.50 MHz (maximum) master bit frequency
5.0 MHz (maximum) slave bit frequency
Four programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Write collision flag protection
Master-master mode fault protection
Easy interface to simple expansion parts (PLLs, D/As, latches,
display drivers, etc.)
Very low clock rates by reuse of the SCI prescalers.
10.3 SPI Signal Description
Three I/O pins located at port B are associated with the SPI data
transfers. They are the serial clock (SCK), the master in/slave out
(MISO) data line, the master out/slave in (MOSI) data line. When the SPI
system is not utilized (SPE bit cleared in the serial peripheral control
register), the three pins (MISO, MOSI, SCK) are configured as general-
purpose I/O pins. The three SPI signals are discussed in the following
paragraphs for both master mode and slave mode of operation.
NOTE:
The SPI subsystem works as master and does not have a slave select
input line (SS).
10.3.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.