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Serial Communications Interface (SCI)
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
132
Serial Communications Interface (SCI)
MOTOROLA
11.5 Receive Data (RDI)
Receive data is the serial data that is applied through the input line and
the serial communications interface to the internal bus. The receiver
circuitry clocks the input at a rate equal to 16 times the baud rate and this
time is referred to as the RT clock.
Once a valid start bit is detected the start bit, each data bit and the stop
bit are sampled three times at RT intervals 8 RT, 9 RT and 10 RT (1 RT
is the position where the bit is expected to start), as shown in
Figure 11-
3
. The value of the bit is determined by voting logic which takes the value
of the majority of the samples.
Figure 11-3. Sampling Technique Used On All Bits
11.6 Start Bit Detection
When the RDI input is detected low, it is tested for three more sample
times (referred to as the start edge verification samples in
Figure 11-4
).
If at least two of these three verification samples detect a logic zero, a
valid start bit has been detected, otherwise the line is assumed to be idle.
A noise flag is set if all three verification samples do not detect a logic
zero. A valid start bit could be assumed with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros
for 8-bit format or 11 zeros for 9-bit format), the circuit continues to
operate as if there actually was a stop bit and the start edge will be
placed artificially. The last bit received in the data shift register is
PREVIOUS BIT
PRESENT BIT
SAMPLES
NEXT BIT
RDI
V
V
V
16
R
T
1
R
T
8
R
T
9
R
T
10
R
T
16
R
T
1
R
T