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CPU and Instruction Set
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
40
CPU and Instruction Set
MOTOROLA
The ten most significant bits of the stack pointer are permanently fixed
at 000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.
3.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The two most significant bits
of the program counter are ignored internally.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
3.3.5 Condition Code Register
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed. The following paragraphs describe the
functions of the condition code register.
Bit 15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
–
–
Reset
–
–
Loaded with vector from $3FFE AND $3FFF
Figure 3-5. Program Counter
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
H
I
N
C
Z
Reset
1
1
1
U
1
U
U
U
Figure 3-6. Condition Code Register