16-Bit Timers
Registers
MC68HC(7)05H12
—
Rev. 1.0
General Release Specification
MOTOROLA
16-Bit Timers
105
L
G
R
9.3 Registers
9.3.1 Counter
The key element in the programmable timer is a 16-bit, free-running
counter or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations, $28–$29 (counter register) or $2A–$2B (counter alternate
register). A read from only the least significant byte (LSB) of the free-
running counter ($29, $2B) receives the count value at the time of the
read. If a read of the free-running counter or counter alternate register
first addresses the most significant byte ($28, $2A), the LSB ($29, $2B)
is transferred to a buffer. This buffer value remains fixed after the first
MSB read, even if the user reads the MSB several times. This buffer is
accessed when reading the free-running counter or counter alternate
Addr
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
Register Name
Timer1 Capture 1 High
Timer1 Capture 1 Low
Timer1 Compare 1 High
Timer1 Compare 1 Low
Timer1 Capture 2 High
Timer1 Capture 2 Low
Timer1 Compare 2 High
Timer1 Compare 2 Low
Timer1 Counter High
Timer1 Counter Low
Timer1 Alternate Counter High
Timer1 Alternate Counter Low
Timer1 Control 1
Timer1 Control 2
Timer1 Status
Figure 9-2. 16-Bit Timer Register Addresses (Timer1)