Input/Output Ports
Port E and Port F (Power Drivers)
MC68HC(7)05H12
—
Rev. 1.0
General Release Specification
MOTOROLA
Input/Output Ports
89
L
G
R
The actual output level POUT of a single power driver is compared with
the set output level SOUT via the EXOR gate in the circuitry. The buffer
C provides ‘low’ if the ‘high’ set output is significantly lower than PVDD
or it provides a ‘high’ if the ‘low’ set output is significantly higher than
PVSS. The comparison result is latched with the appropriate signal SYN
which runs at bus frequency. The timing of the signal SYN depends on
the amount of microshifts for the actual PWM channel. The SYN signal
occurs 1/4 of a bus cycle later than the start of the PWM period. This
ensures the PWM signal being stable on the output POUT. A mismatch
between the levels SOUT and POUT which indicates a short circuit on
the output results in a ‘high’ signal latched by the HFF. This latched
mismatch signal MISL is now stored in the corresponding bit MR of the
mismatch register. The mismatch register of port E or port F can be
polled in a proper time period like an interrupt flag register. A read ‘high’
on the mismatch register bit has to be handled like an interrupt flag. It will
be cleared by writing a logic ‘1’ back to this register.
7.7.5 Port E and Port F Mismatch Registers
Bit 7–0 — Port E short circuit indication
The bits 7–0 indicate a short circuit on the port E. Each bit is cleared
by writing a ‘1’ to it.
1 = Short circuit at the corresponding port E pin
0 = No short circuit at the corresponding port E pin
$0041
Bit 7
6
5
4
3
2
1
Bit 0
Read:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 7-9. Port E Mismatch Register (PEMISM)