L
G
R
Input/Output Ports
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
82
Input/Output Ports
MOTOROLA
7.3.4 Port A Interrupt Status Register
PAIF7–0 — Port A Interrupt Flags
These flags indicate which of the port A interrupt requests is pending.
The 8 interrupt flags can be reset individually if a ‘1’ is written to the
bit position.
1 = Flag set when corresponding transition is sensed (even if
interrupt is disabled), writing ‘1’ clears the flag
0 = No interrupt
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001,
the port B data direction register (DDR) is at $0005. Reset does not
affect the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. The port pins PB5–PB7 are
shared with the SPI system (MISO, MOSI, SCK). If the SPI system is
enabled the pins PB5–PB7 are connected to the SPI system.
Pin PB2 is shared with the internal system clock ECLK. If the ECLK bit
in the system option register is set the internal system clock is available
through PB2 independently of the value of the port B data direction
register. Refer to
Section 2.3.1 System Control Register
for more
information. When the ECLK bit is set to ‘1’ the port B data direction
register can still be read or written, but does not impact the ECLK
function at pin PB2. When the ECLK bit is set to ‘1’ the port B data
register bit 2 loses its contents and is not accessible.
$000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PAIF7
PAIF6
PAIF5
PAIF4
PAIF3
PAIF2
PAIF1
PAIF0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 7-3. Port A Interrupt Status Register (PAISR)