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Interrupts
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
60
Interrupts
MOTOROLA
4.2 Introduction
The MCU can be interrupted eight different ways:
1.
2.
3.
4.
5.
6.
7.
8.
Nonmaskable Software Interrupt Instruction (SWI)
External Asynchronous Interrupt (IRQ)
External Keyboard Wakeup on Port A
Internal 8 bit Timer Interrupt (CTIMER)
Internal 16-bit Timer1 Interrupt (TIMER1)
Internal 16-bit Timer2 Interrupt (TIMER2)
Internal Serial Communications Interface Interrupt (SCI)
Internal Serial Peripheral Interface Interrupt (SPI)
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I-bit) to prevent additional interrupts.
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the
corresponding interrupt enable bit is set, then the processor will proceed
with interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs the processor completes the current
instruction, then stacks the current CPU register states, sets the I-bit to
inhibit further interrupts, and finally checks the pending hardware
interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in
Table 4-1
will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
When an interrupt is to be processed the CPU fetches the address of the
appropriate interrupt software service routine from the vector table at
locations $3FF0 to $3FFF as defined in
Table 4-1
.