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參數(shù)資料
| 型號(hào)： | P32P4910A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | PRML Read Channel with PR4, 8/9 ENDEC, 4-Burst Servo |
| 中文描述： | READ CHANNEL, PQFP100 |
| 文件頁(yè)數(shù)： | 108/196頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | P32P4910A |
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L
G
R
16-Bit Timers
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
106
16-Bit Timers
MOTOROLA
register LSB ($29 or $2B) and thus completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB must also be read to
complete the sequence.
The counter alternate register differs from the counter register in one
respect: a read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
9.3.2 Output Compare Registers
There are two output compare registers: output compare register 1 and
output compare register 2. Output compare registers can be used for
several purposes such as controlling an output waveform or indicating
when a period of time has elapsed. All bits are readable and writable and
are not altered by the timer hardware or reset. If the compare function is
not needed, the two bytes of the output compare register can be used as
storage locations.
9.3.3 Output Compare Register 1
The 16-bit output compare register 1 is made up of two 8-bit registers at
locations $22 (MSB) and $23 (LSB). The output compare register
contents are compared with the contents of the free-running counter
once every four internal processor clock cycles. If a match is found, the
output compare flag OC1F (bit 5 of the timer status register ($2E)) is set
and the corresponding output level OLVL1 bit is clocked to TCMP1
output.
The output compare register values and the output level bit should be
changed after each successful comparison to establish a new elapsed
time-out. An interrupt can also accompany a successful output compare
provided the corresponding interrupt enable bit (OCI1E) is set.
After a processor write cycle to the output compare register 1 containing
the MSB ($22), the output compare function is inhibited until the LSB
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| P32P4911A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PRML Read Channel with PR4, 8/9 ENDEC, FWR Servo |
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