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Serial Peripheral Interface (SPI)
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
120
Serial Peripheral Interface (SPI)
MOTOROLA
status bits. A single status bit (SPIF) is used to signify that the I/O
operation has been completed.
The SPI is double buffered on read, but not on write. If a write is
performed during data transfer, the transfer is not interrupted, and the
write will be unsuccessful. This condition will cause the write collision
status bit (WCOL) in the SPSR to be set. After a data byte is shifted, the
SPIF flag in the SPSR is set.
In master mode, the SCK pin is an output. It idles high or low, depending
on the CPOL bit in the SPCR, until data is written to the shift register.
Then eight clocks are generated to shift the eight bits of data, after which
SCK goes idle again.
In slave mode, the slave start logic receives a clock input at the SCK pin.
Thus, the slave is synchronized to the master. Data from the master is
received serially via the slave MOSI line and is loaded into the 8-bit shift
register. The data is then transferred, in parallel, from the 8-bit shift
register to the read buffer. During a write cycle, data is written into the
shift register, then the slave waits for a clock train from the master to shift
the data out on the slave’s MISO line.
Figure 10-3
illustrates the MOSI, MISO and SCK master-slave
interconnections.
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
MOSI
SPI CLOCK
GENERATOR
SCK
SCK
SLAVE
MASTER