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Data Sheet
119
Rev. 1.2, 2006-01-26
QuadFALC
TM
PEF 22554 E
Functional Description E1/T1/J1
3.7
Transmit Path
The transmit path of the QuadFALC
Figure 33
Transmit System of one Channel
Note: DR = Dual-Rail interface
The serial bit stream is processed by the transmitter which has the following functions:
Frame/multiframe synthesis of one of the four selectable framing formats
Insertion of service and data link information
AIS generation (blue alarm)
Remote alarm (yellow alarm) generation
CRC generation and insertion of CRC bits
CRC bits inversion in case of a previously received CRC error or in case of activating per control bit
Generation of loop-up/-down code
Idle code generation per DS0
The frame/multiframe boundaries of the transmitter can be synchronized externally by using the SYPX/XMFS pin.
Any change of the transmit time slot assignment subsequently produces a change of the framing bit positions on
the line side. This feature is required if signaling and data link bits are routed through the switching network and
are inserted in transmit direction by the system interface.
In loop-timed configuration (LIM2.ELT) disconnecting the control of the transmit system highway from the
transmitter is done by setting FMR5.XTM. The transmitter is now in a free running mode without any possibility to
update the multiframe position in case of changing the transmit time slot assignment. The FS/DL-bits are
generated independent of the transmit system interface. For proper operation the transmit elastic buffer size
should be programmed to 2 frames.
The contents of selectable time slots is overwritten by the pattern defined by register IDLE. The selection of “idle
channels” is done by programming the three-byte registers ICB(3:1).
If AMI coding with zero code suppression (B7-stuffing) is selected, “clear channels” without B7-stuffing can be
defined by programming registers CCB(3:1).
Pulse
Shaper,
LBO
Framer
and
Encoder
XDATA
XCLK
XL2/XDON
DCO-X
Transmit Elastic Buffer
MCLK
QFALCv3_ITS10305
Transmit Line
Interface
E: performedby multiplexers 1" and2" in system interface
F: controlledby CMR1.DXSS andautomatic transmit clock switching
G: controlledby LIM1.RL,JATT andLIM2.ELT
H: controlledby SIC1.XBS(1:0), CMR1.DJXA and automatic transmit clock switching
%: divider: for GPC6.COMP_DIS = 0 controlledby CMR6.STF(2:0)
for GPC6.COMP_DIS= 1 controlled by CMR1.STF
Master
Clocking Unit
DAC
DR DR
XL1/XDOP/XOID
G
H
E
F
%
SCLKR
TCLK
SCLKX
Automatic Transmit
Clock Switching
recovered
receive clock
internal
transmit
clock
from
DCO-R