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QuadFALC
TM
PEF 22554 E
Functional Description E1/T1/J1
Data Sheet
106
Rev. 1.2, 2006-01-26
3.6
Receive Path
An overview about the receive path of one channel of the QuadFALC
Figure 24
Receive System of one Channel
The recovered clock selection of Figure 24 (multiplexer “A”) is shown in more detail for compatibility mode in
The multiplexer “C” in Figure 24 selects the mode of the receive jitter attenuator, see chapter Chapter 3.6.5.
The multiplexer “D” in Figure 24 selects if the receive clock RCLK of a channel is sourced by the recovered route
clock or by the DCO-R (see above). The appropriate register bits are CMR1.RS(1:0) (CMR1_E) in compatibility
mode or CMR4.RS(2:0) (CMR4_E) in generic mode. These register bits also select different DCO-R output
frequencies.
The sources of the receive clock output pins (RCLK(4:1)), configured by the multi function ports, can be selected
out of the receive clocks of the channels:
For GPC6.COMP_DIS = 1
B the source of each of the four receive clock pins (RCLK(4:1)) can be independently
selected out of each of the four receive clocks of the channels by programming the registers bits GPC(2:6).RS(2:0)
B the register bits GPC1.RS(1:0) are
not valid for selection of the receive clock, see also Table 65.
For GPC6.COMP_DIS = 0
B the source of the RCLK1 pin can only be selected by the register GPC1 (GPC1_E), see multiplexer “B” in Figure 25. The sources of the pins RCLK2,3,4 are the appropriate channel receive clocks.
After reset pin RCLK1 is sourced by the receive clock of channel 1 and is switched to the multi function ports RPC.
The registers GPC2 to GPC6 are not valid if GPC6.COMP_DIS = 0
B.
Note that in channel translation (CT) mode the DCO-R is always on.
Equalizer
Clock &
Data
Recovery
Framer
and
Decoder
Alarm
Detector
Analog
LOS
Detector
RDATA
RCLK
SYNC
RL1/RDIP/ROID
RL2/RDIN/RCLKI
DCO-R
Receive Elastic Buffer
MCLK
QFALCv3_F0117
Recovered
clock selection
from other
channels
ReceiveLine
Interface
DPLL
A
C
A: for GPC6.COMP_DIS = 1 controlledby CMR1.DRSS(1:0)
for GPC6.COMP_DIS = 0 controlledby CMR5.DRSS(2:0)
C: controlledby CMR1.DCS andLIM0.MAS
D: for GPC6.COMP_DIS= 1controlledby CMR1.RS(1:0)
for GPC6.COMP_DIS = 0 controlledby CMR4.RS(2:0)
1: multiplexer 1" insystem interface, controlledby CMR2.IRSC
and SIC1.RBS(1:0)
D
Master
Clocking Unit
LOS
1
SCLKR
internal
receive clock
recovered
receive clock