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Data Sheet
467
Rev. 1.2, 2006-01-26
QuadFALCTM
PEF 22554 E
T1/J1 Registers
Synchronization/Resynchronization Procedure (F12/F72)
Specified number of errors in FT framing has the same effect as above. Specified number
of errors in FS framing only initiates a new search for multiframe alignment without
influencing pulseframe synchronous state (FRS0.LMFA is set).
01B
Synchronization/Resynchronization Procedure (F12)
(not in F72 format) A one enables a synchronization mode which is able to choose multiple
framing pattern candidates step by step. I.e. if in synchronous state the CRC error counter
indicates that the synchronization might have been based on an alias framing pattern, setting
of FMR0.FRS leads to synchronization on the next candidate available. However, only the
previously assumed candidate is discarded in the internal framing pattern memory. The
latter procedure can be repeated until the framer locks on the right pattern (no extensive
CRC errors). Therefore bit FMR1.CRC must be set.
10B
Table 112
MCSP/SSP Constant Values (Case 2)
Name and Description
Value
Synchronization/Resynchronization Procedure (F24)
normal operation: synchronization is achieved only on verification the framing pattern.
00B
Synchronization/Resynchronization Procedure (F24)
Synchronous state is reached when three consecutive multiframe pattern are correctly found
independent of the occurrence of CRC6 errors.
01B
Synchronization/Resynchronization Procedure (F24)
A one enables a synchronization mode which is able to choose multiple framing pattern
candidates step by step. I.e. if in synchronous state the CRC error counter indicates that the
synchronization might have been based on an alias framing pattern, setting of FMR0.FRS
leads to synchronization on the next candidate available. However, only the previously
assumed candidate is discarded in the internal framing pattern memory. The latter
procedure can be repeated until the framer locks on the right pattern (no extensive CRC
errors). Therefore bit FMR1.CRC must be set.
10B
Synchronization/Resynchronization Procedure (F24)
Synchronization is achieved on verification the framing pattern and the CRC6 bits.
Synchronous state is reached when framing pattern and CRC6 checksum are correctly
found. For correct operation the CRC check must be enabled by setting bit FMR1.CRC.
11B
Table 111
MCSP/SSP Constant Values (Case 1) (cont’d)
Name and Description
Value