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Data Sheet
75
Rev. 1.2, 2006-01-26
QuadFALC
TM
PEF 22554 E
Pin Descriptions
D2
RPA1
I
PU
Synchronous Pulse Receive, port 1
SYPR, PC(1:4).RPC(3:0) = 0000
B
Together with the values of registers RC(1:0) this signal
defines the beginning of time slot 0 on system highway port
RDO.
Only one multifunction port may be selected as SYPR input.
After reset, SYPR of port A is used, the other lines are
ignored.
In system interface multiplex mode, SYPR has to be provided
at port RPA1 for four or all four channels dependent if 4:1 or
8:1 multiplex mode is selected. SYPR defines the beginning
of the time slot 0 on port RDO/RSIG.
The pulse cycle is an integer multiple of 125
s.
D3
RPB1
D1
RPC1
D4
RPD1
D2
RPA1
O
–
Receive Frame Marker (RFM), port 1
PC(1:4).RPC(3:0) = 0001
B
CMR2.IRSP = 0
The receive frame marker can be active high for a 2.048 MHz
(E1) or 1.544 MHz (T1/J1) period during any bit position of
the current frame. It is clocked off with the rising or falling
edge of SCLKR or RCLK, depending on SIC3.RESR. Offset
programming is done by using registers RC(1:0).
CMR2.IRSP = 1
Frame synchronization pulse generated by the DCO-R
circuitry internally. This pulse is active low for a 2.048 MHz
(E1) or 1.544 MHz (T1/J1) period.
D3
RPB1
D1
RPC1
D4
RPD1
D2
RPA1
O
–
Receive Multiframe Begin (RMFB), port 1
PC(1:4).RPC(3:0) = 0010
B
In E1 mode RMFB marks the beginning of every received
multiframe (RDO). Optionally the time slot 16 CAS
multiframe begin can be marked (SIC3.CASMF). Active high
for one 2.048 MHz period.
In T1/J1 mode the function depends on bit XC0.MFBS:
MFBS = 1
RMFB marks the beginning of every received multiframe
(RDO).
MFBS = 0
RMFB marks the beginning of every received superframe.
Additional pulses are provided every 12 frames when using
ESF/F24 or F72 format.
D3
RPB1
D1
RPC1
D4
RPD1
D2
RPA1
O
–
Receive Signaling Marker (RSIGM), port 1
PC(1:4).RPC(3:0) = 0011
B
E1: Marks the time slots which are defined by register
RTR(4:1) of every received frame on port RDO.
T1/J1: Marks the time slots which are defined by register
RTR(4:1) of every received frame on port RDO, if CAS-BR is
not used.
When using the CAS-BR signaling scheme, the robbed bit of
each channel every sixth frames is marked, if CAS-BR is
enabled by XC0.BRM = 1
B.
D3
RPB1
D1
RPC1
D4
RPD1
Table 2
I/O Signals for P/PG-LBGA-160-1 (cont’d)
Ball No. Name
Pin Type
Buffer
Type
Function