
QuadFALCTM
PEF 22554 E
E1 Registers
Data Sheet
400
Rev. 1.2, 2006-01-26
Interrupt Status Register 1
All bits are reset when ISR1 is read. If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are
masked by register IMR1. However, these masked interrupt statuses neither generate a signal on INT (or INT1,
ISR1_E
Offset
Reset Value
Interrupt Status Register 1
xx69H
00H
Field
Bits
Type
Description
LLBSC
7
rsc
Line Loop-Back Status Change
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM = 0B: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10-2. The LLBSC bit is also set, if the current
detection status is left, i.e., if the bit error rate exceeds 10-2. The actual
detection status can be read from the RSP.LLBAD and RSP.LLBDD,
respectively.
PRBS Status Change LCR1.EPRM = 1B: With any change of state of
the PRBS synchronizer this bit is set. The current status of the PRBS
synchronizer is indicated in RSP.LLBAD.
RDO
6
rsc
Receive Data Overflow - HDLC Channel 1
This interrupt status indicates that the external micro controller did not
respond fast enough to an RPF or RME interrupt and that data in RFIFO
has been lost. Even when this interrupt status is generated, the frame
continues to be received when space in the RFIFO is available again.
Note: Whereas the bit RSIS.RDO in the frame status byte indicates
whether an overflow occurred when receiving the frame currently
accessed in the RFIFO, the ISR1.RDO interrupt status is generated
as soon as an overflow occurs and does not necessarily pertain to
the frame currently accessed by the processor.
ALLS
5
rsc
All Sent - HDLC Channel 1
This bit is set if the last bit of the current frame has been sent completely
and XFIFO is empty. This bit is valid in HDLC mode only.
XDU
4
rsc
Transmit Data Underrun - HDLC Channel 1
Transmitted frame was terminated with an abort sequence because no
data was available for transmission in XFIFO and no XME was issued.
Note: Transmitter and XFIFO are reset and deactivated if this condition
occurs. They are reactivated not before this interrupt status register
has been read. Thus, XDU should not be masked by register IMR1.
Additionally, CMDR.SRES must be set after XDU occurs to reset
the signalling transmitter.