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參數(shù)資料
| 型號(hào)： | PSB7230 |
| 廠商： | SIEMENS A G |
| 元件分類： | 編解碼器 |
| 英文描述： | Joint Audio Decoder-Encoder for Analog Videophone JADE AN |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP100 |
| 文件頁(yè)數(shù)： | 109/179頁(yè) |
| 文件大?。?/td> | 2422K |
| 代理商： | PSB7230 |
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PSB 7230
Register Description
Semiconductor Group
109
Data Sheet 1998-07-01
RSCO
Receive Time-slot Continuous
When RSCO is equal to one, the time-slot capacity (normally given by
register RCCR, between 1 and 256 bits) is
“infinity”. This means that the
time-slot will be always “active” so that data can be permanently received if
RAC = 1.
If RFDIS = 0, and if the time-slot count logic has been reset (by issuing
RRES while RAC = 0), time-slot logic can start operation and thus “activate”
a time-slot only after the first frame sync pulse is detected (i.e. on FSC, RFS,
or TFS, whichever has been selected). The time-slot offset register TSAR +
bit RCS0 mark the instant when the “infinite” time-slot will be activated after
the first frame sync pulse has occurred. If RFDIS = 1, reception can start
immediately, without the necessity to wait for the first frame sync pulse.
Receive Frame Sync Disregard
When RFDIS is “1”, the time-slot generation logic disregards frame syncs.
In particular, if RSCO = 1 and RFDIS = 1, receive time-slot is immediately
considered as permanently “active”, and remains activated as long as this
condition prevails.
Transmit Time-slot Continuous
When TSCO is equal to one, the time-slot capacity (normally given by
register XCCR, between 1 and 256 bits) is “infinity”. This means that the
time-slot will be always “active” so that data can be permanently transmitted
if XAC = 1.
If TFDIS = 0, and if the time-slot count logic has been reset (by issuing
XRES while XAC = 0), time-slot logic can start operation and thus “activate”
a time-slot only after the first frame sync pulse is detected (i.e. on FSC, RFS,
or TFS, whichever has been selected). The time-slot offset register TSAX +
bit XCS0 mark the instant when the “infinite” time-slot will be activated after
the first frame sync pulse has occurred. If TFDIS = 1, transmission can start
immediately, without the necessity to wait for the first frame sync pulse.
Transmit Frame Sync Disregard
When TFDIS is “1”, the time-slot generation logic disregards frame syncs. In
particular, if TSCO = 1 and TFDIS = 1, transmit time-slot is immediately
considered as permanently “active”, and remains activated as long as this
condition prevails.
RFDIS
TSCO
TFDIS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSB7238 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder - Multimode |
| PSB7238FV2.1JADEMM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder |
| PSB7280FV3.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280FV3.1D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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