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參數(shù)資料
| 型號(hào)： | PSB7230 |
| 廠商： | SIEMENS A G |
| 元件分類： | 編解碼器 |
| 英文描述： | Joint Audio Decoder-Encoder for Analog Videophone JADE AN |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP100 |
| 文件頁數(shù)： | 65/179頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | PSB7230 |
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PSB 7230
Functional Blocks
Semiconductor Group
65
Data Sheet 1998-07-01
The received data is stored in the receive FIFO so that byte alignment in the FIFO
corresponds to byte alignment in the serial time-slot (if the length of the time-slot is a
multiple of 8 bits). Similarly, in transmit direction the byte alignment in the FIFO
corresponds to the time slot boundaries in the transmit time-slot, if its length is a multiple
of 8 bits. When the transmit FIFO is empty, idle (
“1”) is transmitted during the active time-
slot. Outside the selected time-slot, the output line is in “high impedance” state.
Details on the Operation of the Serial Data Receiver
The data receive FIFO size is 2
×
32 bytes. One half of the FIFO is connected to the
receiver shift register while the second half is accessible from the controlling software.
The status bits pertaining to the data receiver are:
The data receiver is controlled by the following bits:
Details on the Operation of the Serial Data Transmitter
The transmit FIFO size is 2
×
32-bytes. One half is connected with the transmit shift
register while the other half is accessible via the controlling software.
The interrupt status bits pertaining to the data transmitter are:
RPF
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame has not yet
been completely received.
Signifies that data has been lost because no room was available in RFIFO.
RFO
RAC
Receiver Active
When RAC is set to “1”, storage of bytes in the receive FIFO starts time-slot
aligned (if the receive time-slot length is a multiple of 8 bits).
Receive Message Complete
Acknowledges a previous RPF status. Frees the FIFO pool for the next
received frame or part of a frame.
Receiver Reset
Resets the data receiver, which goes into an idle state (RAC cleared), clears
the receive FIFO.
RMC
RRES
XPR
Transmit Pool Ready
One data block may be entered into the transmit FIFO.
All Sent.
When “1”, indicates that the last bit has been transmitted and that the XFIFO
is empty.
ALLS
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相關(guān)代理商/技術(shù)參數(shù) |
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| PSB7238 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder - Multimode |
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| PSB7280 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder |
| PSB7280FV3.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280FV3.1D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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