
PSB 7230
Functional Blocks
Semiconductor Group
74
Data Sheet 1998-07-01
4.4.2
The two C/I channels are controlled via the C/I Transmit (CIX) and C/I Receive (CIR)
registers, the C/I channel Enable (CIEN) and the C/I Change (CIC) interrupt status bit.
In addition, an Awake (AWK) control bit is provided. When this bit is set to
“1”, the output
line is unconditionally “l(fā)ow” until AWK is set to “0” again. This bit is used in ISDN terminal
applications to “wake up” the IOM-2 interface, i.e. to require clocking to be generated on
DCL and FSC by an upstream circuit - typically an ISDN S-Bus Access Controller
ISAC-S.
When the AWK bit is set to “0”, the output line is released only after the next FSC pulse
has been detected, to avoid sending an invalid code in the outgoing C/I channel. C/I data
reception and processing begins after setting CIEN to 1. It is made sure that no invalid
code is sent or receiced. AWK overrides any data normally transmitted during the C/I
time-slot even if CIEN = 1. When CIEN (synchronized with FSC) is “0” and AWK
(synchronized with FSC) is “0”, the outgoing C/I channel is permanently in
high-impedance state.
The block diagram of the C/I channel handler is shown below.
In the receive direction, a change is recognized either using Double Last Look (DLL = 1)
or not (DLL = 0).
C/I Channel
Without Double Last Look
A change in received C/I channel is recognized after a new value is recognized once.
The new value is loaded into CIR for the DSP to read, and a CIC interrupt status is
generated.
If further changes in receive C/I code take place before a previous changed value in CIR
has been read, the changed values are not loaded in CIR.
When the first changed value is read by the DSP, the latest changed value is loaded in
CIR and a CIC interrupt status is generated anew. Any possible changes that occurred
between the first and the latest are thus lost.