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參數(shù)資料
| 型號(hào)： | PSB7230 |
| 廠商： | SIEMENS A G |
| 元件分類： | 編解碼器 |
| 英文描述： | Joint Audio Decoder-Encoder for Analog Videophone JADE AN |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP100 |
| 文件頁數(shù)： | 116/179頁 |
| 文件大?。?/td> | 2422K |
| 代理商： | PSB7230 |
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PSB 7230
Firmware Features
Semiconductor Group
116
Data Sheet 1998-07-01
The following steps are executed:
For the restart of the internal firmware the JADE AN needs the same initialization time
like after a hardware reset. So, the user should wait for 10 ms before it accesses the
JADE AN again.
6.1.3
In case the JADE is not currently needed in the system, the device can be powered
down. Two options exists, one power-down including the PLL and one excluding it.
These options are selected via the contents of the control register 60
H
. A non-zero value
leaves the PLL powered-up while the rest of the JADE goes power-down and a zero
value in register 60
H
includes the PLL in the power-down sequence and therefore is a
complete power-down of the chip.
The power-up is triggered by one of the following interrupts: GPIO, Host interrupt and C/I
channel interrupt.
The sequence to power-down the device is as follows:
1. The host initializes the control registers 60
H
by writing a ‘0’ or a non-zero value into it
(PLL included or excluded, see above).
2. The host generates an interrupt to the JADE by writing value 37
H
into INH interrupt
status register at address 50
H
.
3. The JADE resets the INHB bit. There is no further acknowledge to this interrupt since
the JADE will go to power-down almost immediately.
4. The host may reset the INDB as a reaction to the JADE interrupt. This step is not
mandatory and may be skipped.
5. The JADE firmware disables the CLKO pin, the PLL as selected and the DSP and can
be woken up by any of the above mentioned interrupts. If the PLL was powered down,
it takes longer to resume normal operation. If the PLL remained powered up, the
firmware is immediately ready for resuming operation.
Power Down Command
1.
2.
The host initializes the control registers 60
H
and 61
H
by writing a “0” into it.
The host generates an interrupt to the JADE by writing value 12
H
into INH
interrupt status register at address 50
H
The JADE resets the INHB bit and acknowledges the reception by generating
an interrupt at INT# line to the host by writing a value 13
H
into IND interrupt
status register at address 58
H
.
The host may reset the INDB as a reaction to the JADE interrupt. This step is
not mandatory and may be skipped.
The JADE restarts its internal firmware beginning with the initialization phase.
3.
4.
5.
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| PSB7238 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder - Multimode |
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