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參數(shù)資料
| 型號： | PSB7230 |
| 廠商： | SIEMENS A G |
| 元件分類： | 編解碼器 |
| 英文描述： | Joint Audio Decoder-Encoder for Analog Videophone JADE AN |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP100 |
| 文件頁數(shù)： | 57/179頁 |
| 文件大小： | 2422K |
| 代理商： | PSB7230 |
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PSB 7230
Functional Blocks
Semiconductor Group
57
Data Sheet 1998-07-01
Serial Data Channel Transfer
The interface between the input of the serial data receiver and the DSP or host, and
between the output of the transmitter and DSP or host is in each case a 32-bit long shift
register.
Receiver in LMOD(1:0) = 01, 10, 11
In receive direction, when the shift register from the serial line is filled to a programmable
level (1, 2 or 4), the whole 32-bit shift register is loaded into the HRR1/2 read registers,
physically separate for DSP and host. In the same cycle the contents of the HRW1/2
write register accessible from the DSP (if HHR1/2 = 0) or host (HHR1/2 = 1) are loaded
to the HDLC receiver input. In the next cycle the data from HRR1/2 is as a default loaded
into HRW1/2 and a maskable interrupt status BFHR1/2 is generated to the DSP and
host. The interrupt status is generated to both DSP and host, independent of the setting
of HAH1/2. If the data in HRR1/2 is to be pre-processed, the HRW1/2 register can be
overwritten by the DSP or host before the next 1, 2 or 4 bytes (programmable) have been
shifted into the shift register.
After reset (RRES) when starting the receiver (RAC = 1), the reset status data of HRW
and HRR is ignored by the receiver, i.e. the contents of HRW1/2 and HRR1/2 are not
forwarded to the HDLC receiver, but only the data received from the line. The same
applies to the interrupts: A BFHR1/2 interrupt is only generated after the first 1, 2 or
4 bytes of line data are available in the HRR1/2 register. Due to this pipeline, a latency
occurs in the HDLC/transparent serial data reception, see section below.
The start of the reception can be in the same frame (w.r.t. the frame sync signal on the
chosen line) as the setting of RAC = 1 since the time-slot count logic works
independently of RAC.
In transparent mode (TMO = 1) the reception is only started at the beginning of the time-
slot (time-slot aligned). If RAC is set to ‘1’ during the selected time-slot, the receiver waits
for the beginning of the time-slot in the next frame.
Receiver in LMOD(1:0) = 00
The same applies for LMOD = 00, except the pre-processing is not available. The data
from the bit-reversal unit is bypassed to the HDLC receiver. In addition, the loading of
HRR1/2, HRW1/2 and the generation of the interrupt BFHR1/2 is done like in the other
LMODs for observation of the data stream by the DSP or host only. Thus, the
LMOD = 00 is identical with LMOD = 01, except pre-processing is not available and the
receiver latency after reset is shortened, see section below.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PSB7238 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder - Multimode |
| PSB7238FV2.1JADEMM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Joint Audio Decoder-Encoder |
| PSB7280FV3.1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PSB7280FV3.1D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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