
PSB 7230
Register Description
Semiconductor Group
89
Data Sheet 1998-07-01
RFE
RFS Clock Edge
0
When RFS is generated by the PSB 7238 (= output), it changes
its state at the rising edge of the SCLK clock
1
When RFS is generated by the PSB 7238 (= output), it changes
its state at the falling edge of the SCLK clock.
Receive Frame Sync Select (only valid if RFS is output)
(in both cases the polarity is selected by RFPS)
0
Single cycle RFS is generated
1
The data strobe is output on RFS pin. This only affects the RFS
pin, the internal frame sync is generated and is input to the
timeslot count logic of the audio receivers and transmitters
connected to SR and ST line as in case RFSEL = 0. The strobe
signals of all audio receivers and transmitters connected tp SR
and ST line will be combined by logical OR.
RFS polarity select
0
Rising edge marks the beginning of a new frame on the RFS
line.
1
Falling edge marks the beginning of a new frame on the RFS
line. If RFS is an output it is inverted vs. RFPS = 0
Period of RFS pulse generation
Number of repetition of pulses
When RCONT = 0, RREP(9-0) gives the number of pulses (RREP + 1)
to be generated, spaced 16 bits apart (up to 1024 pulses).
When RCONT = 1, RPRD(4-0) gives the spacing of continuously
generated pulses in 16-bit word increments (up to 32).
TFS In
0
TFS is an input
1
TFS is output
Continuous generation of TFS pulses
0
A number of pulses (spaced 16-bit periods from each other)
equal to TREP + 1 (1,
…, 1024) is generated upon an STX
command (see serial data controller register description)
1
When ETFS bit is “1” (see serial data controller register
description), continuous pulses on TFS are generated, spaced
TPRD + 1 (1, …, 32) 16-bit words from each other.
RFSEL
RFPS
RPRD(4-0)/
RREP(9-0)
TFIN
TCONT