參數(shù)資料
型號(hào): PSB7230
廠商: SIEMENS A G
元件分類: 編解碼器
英文描述: Joint Audio Decoder-Encoder for Analog Videophone JADE AN
中文描述: A/MU-LAW, PCM CODEC, PQFP100
文件頁(yè)數(shù): 29/179頁(yè)
文件大?。?/td> 2422K
代理商: PSB7230
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PSB 7230
Interfaces and Memory Organization
Semiconductor Group
29
Data Sheet 1998-07-01
Channels
The following channels may be programmed on the IOM-2 interface: one receive audio
channel, one transmit audio channel, one Monitor channel, two C/I channels, one
receive and one transmit data channel:
The transfer of voice samples is performed with the help of an interrupt with repetition
rate 8 kHz derived from the FSC signal. A double-buffered register is provided for each
channel, accessible from the DSP and from the parallel host interface. The double
buffered register ensures that enough time is always provided for reading and writing
data before an overflow/underflow occurs, independent of the location of the time-slots.
Alternatively, the audio samples can be transferred between the DSP or Host and IOM-2
by using an interrupt generated when a programmable number (1
… 32) of bits are
shifted out (number independent of the time-slot length on the line).
Outside the time slots where transmission takes place the DU and DD lines are in high
impedance.
DCL
Bits on DU/DD are clocked out with the rising edge of DCL and
latched in with the falling edge of DCL. Frequency 16 kHz to
4.096 MHz.
Marks the beginning of the physical frame on DU and DD. The first
bit in the frame is output after the rising edge of FSC. The first bit in
the frame is latched in with the first falling edge after FSC has gone
“high” if CRS = 1, or after the second edge (at 3/4) if CRS = 0.
FSC (8 kHz)
Audio receive channel
Audio transmit channel
Independently programmable on DD or
DU, with programmable locations (start at
bit 1 … 512) and lengths (1 … 32 bits)
w.r.t. FSC
Programmable on DD(in)/DU(out) or
DD(out)/DU(in), with programmable
time-slot (3rd byte in multiplex 0 … 15)
after FSC
Programmable on DD(in)/DU(out) or
DD(out)/DU(in), with programmable length
(4 or 6 bits) and position (4th byte in
multiplex 0 … 15) after FSC
Independently programmable on DD or
DU, with programmable locations (start at
bit 1 … 512) and lengths (1 … 256 bits)
w.r.t. FSC
Monitor channel
Two C/I channels
Data receive and transmit channels
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