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| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時隙交換器 |
| 文件頁數(shù)： | 13/92頁 |
| 文件大小： | 1450K |
| 代理商： | T8100 |
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Lucent Technologies Inc.
11
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
1 Product Overview
(continued)
1.6 Onboard PLLs and Clock Monitors
The T8100 uses rate multipliers and state machines to
generate onboard frequencies for supporting the
H.100, H-MVIP MVIP MC-1, and SC-Buses. Pins are
provided for coupling the internal clock circuitry with
commonly available clock adapters and jitter attenua-
tors. If external resources are not available, an internal
digital phase-locked loop (DPLL) can be used to gener-
ate all the bus frequencies and remain synchronized to
an 8 kHz reference. One of several clock input refer-
ence sources may be selected, and separate input-
active detection logic can identify the loss of the individ-
ual input references. The entire clocking structure oper-
ates from a 16.384 MHz crystal or external input.
1.7 Phase Alignment of Referenced and
Generated Frames
If this resource is selected, special control logic will cre-
ate bit-sliding in the data streams when the reference
frame and generated frame are out of phase. The bit-
sliding refers to removing a fraction of a bit time per
frame until the frames are in phase.
1.8 Interfaces
1.8.1 Microprocessors
The T8100 provides the user a choice of either Motor-
ola or Intelinterfacing through an 8-bit data bus, a 2-bit
address bus, and multifunction control pins. All access
to T8100 memory blocks and registers use indirect
addressing.
1.8.2 Framing Groups
Two groups of programmable framing signals are avail-
able. Each group is composed of 12 sequenced lines
operating in one of four modes. The T8100 supports
1-bit, 2-bit, 1-byte, and 2-byte pulse widths. Starting
position of the pulse sequences are also programma-
ble.
1.8.3 General-Purpose Register and I/O
A general-purpose register is provided as either a byte-
wide input or byte-wide output through a separate set
of pins.
1.9 Applications
I
Computer-telephony systems
I
Enhanced service platforms
I
WAN access devices
I
PBXs
I
Wireless base stations
1.10 Application Overview
The integration of computers and telecommunications
has enabled a wide range of new communications
applications and has fueled an enormous growth in
communications markets. A key element in the devel-
opment of computer-based communications equipment
has been the addition of an auxiliary telecom bus to
existing computer systems. Most manufacturers of
high-capacity, computer-based telecommunications
equipment have incorporated some such telecom
bus in their systems. Typically, these buses and bus
interfaces are designed to transport and switch
N x 64 kbits/s low-latency telecom traffic between
boards within the computer, independent of the com-
puter’s I/O and memory buses. At least a half dozen of
these PC-based telecom buses emerged in the early
1990s for use within equipment based on ISA/EISA
and MCA computers.
With the advent of the H.100 bus specification by the
Enterprise Computer Telephony Forum, the computer-
telephony industry has agreed on a single telecom bus
for use with PCI and compact PCI computers. H.100
facilitates interoperation of components, thus providing
maximum flexibility to equipment manufacturers, value-
added resellers, system integrators, and others build-
ing computer-based telecommunications applications.
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