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| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時(shí)隙交換器 |
| 文件頁數(shù)： | 41/92頁 |
| 文件大?。?/td> | 1450K |
| 代理商： | T8100 |
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Lucent Technologies Inc.
39
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Descrip-
tion
(continued)
2.4 Clocking Section
(continued)
2.4.3 State Machines
The purpose of the state machines is to generate
internal control signals for the remainder of the T8100
circuitry and to provide all bus clocks when operating
as a master. The state machines operate from the
65.536 MHz clock generated by PLL #1, and they are
time referenced to the frame sync derived from the
selected clock and frame inputs. As a master, the time
sync is based on the T8100’s own generated frame.
The dominant internal control signals are a noninverted
32.768 MHz clock, an inverted 16.384 MHz state clock,
and a noninverted 122 ns wide sync pulse centered
around the beginning of a frame. The memories are
synchronized to the 65.536 MHz clock.
2.4.4 Bit Sliding (Frame Locking)
The T8100 generates its own frame signal based on
the incoming clock and frame references and its gener-
ated clock signals. When slaving, it is sometimes nec-
essary to align the edges of this generated frame
signal to the incoming frame reference.
To accomplish this, the T8100 will compare the
referenced frames with the current state of its clock
state machine, and if the difference exceeds one
65.536 MHz clock cycle, the entire stream will have a
fraction of a bit time removed from each frame; this is
referred to as bit sliding. The process will repeat until
the measurements fall within one clock cycle. The
actual bit sliding will take place by reducing the gener-
ated frame by one 65.536 MHz clock cycle at the
beginning of the frame. This means that the frame
edges will phase-align at the rate of approximately
15.26 ns per frame. The maximum phase difference is
slightly less than one frame or 124.985 μs. Thus, it will
require approximately 8000 frames, or 1 second, to
phase-align the frame. This is also mean time interval
error (MTIE) compliant; performing phase adjustment
of 162 ns per 1.326 ms of total sample time. Refer to
the MTIE specifications document (ATT 62411).
The alternatives to bit sliding are snap alignment and
no alignment. Snap alignment refers to an instanta-
neous phase alignment, i.e., a reset at the frame
boundary. This mode is common to other devices. If no
alignment is chosen, the T8100’s generated frame is
frequency-locked to the incoming frame sync, but not
phase-aligned.
2.4.5 Clock Fallback
The following conditions must be met before fallback is
initiated:
I
Fallback must be enabled in register CKS.
I
Failure of one or more of the clocks selected through
the CKSEL bits in the CKM register.
I
All clocks which comprise the selection from CKSEL
must be unmasked in register CKW (see Section 2.6
Error Registers).
The T8100 contains a fallback register which enables a
backup set of controls for the clock resources during a
clock failure. In addition, a fallback state machine pro-
vides some basic decision-making for controlling some
of the clock outputs when the feature is enabled. While
slaving to the bus, the primary course of action in fall-
back is the swap between the A-clocks and B-clocks as
the primary synchronization sources. A slave may
become a master only under software control; i.e.,
there is no automatic promotion mechanism. As a mas-
ter, the T8100 can detect its own failures and remove
its clocks from the bus. If it detects a failure on the other
main set (e.g., B master detects failures on the A mas-
ter), then it can assume the role as the primary syn-
chronization source by driving all compatibility clocks
(H-MVIPand SC-Bus). Clock failures are flagged
through the CLKERR1 and CLKERR2 registers (Sec-
tion 2.6 Error Registers). Additional fallback details are
discussed in relationship to the clock registers in the
next section. The divide-by-4 block for XTALIN, shown
in Figure 12, is used only for fallback. See Figure 13 for
a diagram of the basic state machine which controls
the A, B, and C (compatibility) clocks.
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