參數(shù)資料
型號(hào)： T8100
英文描述： H.100/H.110 Interface and Time-Slot Interchanger
中文描述： H.100/H.110接口和時(shí)隙交換器
文件頁(yè)數(shù)： 3/92頁(yè)
文件大?。?/td> 1450K
代理商： T8100
Preliminary Data Sheet
August 1998
Ambassador
TM
T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview
1.1 Introduction
Increasingly, enhanced telephony services are pro-
vided by equipment based on mass-market com-
puter-telephony architectures. The H.100 time-
division multiplexed (TDM) bus has emerged as the
industry standard used in these systems. The
Ambassador T8100 is a single device that provides a
complete interface for H.100/H.110-based systems.
The T8100 will support the newer bus standards,
H-MVIP* and ECTF H.100, but remain downward
compatible with MVIP-90 and Dialogic’s
SC-Bus.
Data can be buffered in either minimum delay or con-
stant delay modes on a connection-by-connection
basis.
The T8100 will take advantage of new technology: it
is based on 0.35 micron feature sizes and a robust
standard-cell library. It utilizes associative memory
(content addressable memories [CAM]) in addition to
traditional static RAM and register file structures for
the connection and data memories. The T8100 oper-
ates on a single 3.3 V supply, but all inputs are 5 V
tolerant and standard TTL output levels are main-
tained.
1.2 Features
I
Complete solution for interfacing board-level cir-
cuitry to the H.100 telephony bus
I
H.100 compliant interface; all mandatory signals
I
Programmable connections to any of the 4096 time
slots on the H.100 bus
I
Up to 16 local serial inputs and 16 local serial
outputs, programmable for 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s operation per CHI
specifications
I
Programmable switching between local time slots,
up to 1024 connections
I
Programmable switching between local time slots
and H.100 bus, up to 256 connections
I
Choice of frame integrity or minimum latency
switching on a per-time-slot basis
— Frame integrity to ensure proper switching of
wideband data
— Minimum latency switching to reduce delay in
voice channels
I
On-chip phase-locked loop (PLL) for H.100, MVIP
or SC-Bus clock operation in master or slave clock
modes
I
Serial TDM bus rate and format conversion
between most standard buses
I
Optional 8-bit parallel input and/or 8-bit parallel
output for local TDM interfaces
I
High-performance microprocessor interface
— Provides access to device configuration regis-
ters and to time-slot data
— Supports both Motorola
nonmultiplexed and
Intel
§
multiplexed/nonmultiplexed modes
I
Two independently programmable groups of up to
12 framing signals each
I
3.3 V supply with 5 V tolerant inputs and TTL-com-
patible outputs
I
Boundary-scan testing support
I
208-pin, plastic SQFP package
I
217-pin BGA package (industrial temperature
range)
* MVIP is a registered trademark of GO-MVIP Inc.
Dialogic s a registered trademark of Dialogic Corporation.
Motorolais a registered trademark of Motorola, Inc.
§ Intel is a registered trademark of Intel Corporation.
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