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參數(shù)資料
| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時隙交換器 |
| 文件頁數(shù)： | 40/92頁 |
| 文件大小： | 1450K |
| 代理商： | T8100 |
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38
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Descrip-
tion
(continued)
2.4 Clocking Section
(continued)
2.4.1 Clock and NETREF Selection
The inputs to the T8100 clocking come from three
selectors. The clock selector and frame selector oper-
ate from a common set of selection options in register
CKM (see Section 2.4.6 Clock Control Register Defini-
tions for register details), where FRAMEA is selected
along with clock C8A and FRAMEB is selected along
with clock C8B. Typically, one of the local references
(LREF[0:7]) will be selected when the T8100 is operat-
ing as a master, though the local oscillator is also avail-
able. As a slave, the most common selections will be
one of the bus types. Each bus type has a state
machine associated with it for determining the frame
sync. All clock inputs are sampled to check for proper
switching. If the expected clock edge does not occur,
and there is no switching on CT_NETREF for 125
μ
s, a
bit corresponding to the errant clock is set in the CLK-
ERR register (see Section 2.6 Error Registers for more
details). NETREF can be created from one of the local
references or from the oscillator independent of the
clock generation.
2.4.2 Dividers and Rate Multipliers
The clock and NETREF selections are routed to divid-
ers*. In the case of NETREF, the divider is
usually used to reduce a bit rate clock to 8 kHz,
so the most common divisors will be 1, 193
(1.544 MHz/8 kHz), and 256 (2.048 MHz/8 kHz),
although a full range of values (from 1—256) is possi-
ble. For the clock selector, the signal will most often be
routed through the main divider when the T8100 is
operating as a master or through the resource divider
when operating as a slave. Both the main and resource
dividers are fully programmable.
The ultimate destination for the main or resource
divider is intended to be PLL #1. PLL #1 accepts either
a 2.048 MHz or 4.096 MHz input and will rate multiply
up to 65.536 MHz. The divisor of the main or resource
dividers is chosen in conjunction with the rate select of
the PLL, i.e., a divisor which generates a 4.096 MHz
output and a rate selection of x16, or a divisor which
generates a 2.048 MHz output and a rate selection of
x32. This provides a great deal of flexibility in adapting
to a variety of (external) clock adapters and jitter atten-
uators while acting as a master, as well as slaving to
several bus types.
A digital PLL that can rate multiply to either 2.048 MHz
or 4.096 MHz from an 8 kHz source in the absence of
an external clock adapter is also provided. PLL #1 can
be bypassed for diagnostic purposes or if an external
clock adapter is used that provides a high-speed output
(65.536 MHz). The input to the DPLL is for an 8 kHz
signal only.
A second rate multiplier is provided for supporting T1
applications. It is optimized around either a 1.544 MHz
or 3.088 MHz input rate which multiplies to 24.704 MHz
and is then divided down to provide 50% duty cycle
clocks of 12.352 MHz, though the direct 24.704 MHz is
available as well. A bypass is provided so that an exter-
nal clock can be buffered through the TCLK output. The
internal oscillator or the various outputs derived from
PLL #1 can also be selected for the TCLK output.
* If the A clocks have been selected as the clock source through the
CKM register (described in Section 2.4.6 Clock Control Register
Definitions), then the CT_C8A is the signal sent to the main and
resource dividers; likewise, selecting B clocks results in sending
CT_C8B; the MVIP selection sends /C4; the H-MVIPselection
sends the recovered /C16 (derived from differential inputs); select-
ing SC2 sends SCLKX2; and SC4/8 sends SCLK to the dividers.
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