參數(shù)資料
型號(hào)： T8100
英文描述： H.100/H.110 Interface and Time-Slot Interchanger
中文描述： H.100/H.110接口和時(shí)隙交換器
文件頁數(shù)： 47/92頁
文件大小： 1450K
代理商： T8100
Lucent Technologies Inc.
45
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Description
(continued)
2.4 Clocking Section
(continued)
2.4.6 Clock Control Register Definitions
(continued)
Table 43. CKS: Clocks, Secondary (Fallback) Selection, 0x04
Clock register 0x04 is CKS, the secondary clock selection register. This is also referred to as fallback. Along with
programming the CKS register, CKW and CKS should be programmed last. The register is defined as follows:
* This bypasses the CRS/FRS multiplexer and is the default condition. It is equivalent to letting the T8100 free run on a clock failure. It assumes
PLL #1 has been set for x16. If PLL #1 is set for x32, then use FCSEL = 8 kHz local reference, FRS = 10, and FTS = 10.
REG
CKS
R/W
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
FF
Bit 2
Bit 1
FCSEL
Bit 0
FRS
FTS
Symbol
FRS
Bit
7—6 FRS provides an alternate clock resource selection. FTS determines the basic fallback mode.
FF forces the use of the FRS, FTS, and FCSEL. FCSEL is used to select an alternate synchro-
nization source.
FRS forces the clock resource selector to choose a new source for PLL #1.
FRS = 00, External input (through the 4 MHz In pin)
FRS = 01, Resource divider
FRS = 10, DPLL @ 2.048 MHz
FRS = 11, DPLL @ 4.096 MHz
Name/Description
Note:
The decode is the same as that of the CRS bits (in the clock resource register, CKR).
5—4 For fallback type select, the two FTS bits are used to enable the automatic fallback. These work
in conjunction with the various clocks as described in Section 2.4.5 Clock Fallback. If the C8
input select (C8IS of the CKP register above) is low, then the T8100 is assumed to be in an
MC-1 system. Thus, the A/B clocks can be interpreted as /C4L (or /C4R) for C8A and /C4R (or
/C4L) for C8B.
FTS = 00,
Fallback from main clock to the oscillator divided by 4* when main clock fails.
(Main clock determined by CKSEL bits of the CKM register.)
FTS = 01,
Fallback disabled; this is not recommended for operation, it is intended for ini-
tialization and diagnostic purposes only.
FTS = 10,
Fallback from main selection to secondary source (FCSEL).
FTS = 11,
Fallback from A or B clock (ECTF/MC-1) to secondary; this also enables the
fallback state machine.
When one of the selected bits goes high in the CLKERR register (i.e., clock failure, see Section
2.6 Error Registers), then clocks are changed to the selection indicated by FCSEL, the A or B
clocks are disabled (if applicable), and the compatibility clocks are either driven or disabled (if
applicable). Note that the change is “sticky”; once the fallback has occurred, it will stay in its
new state until the system is reprogrammed. Clearing the CLKERR registers through the MCR
(Section 2.1.2 Master Control and Status Register) clears the fallback condition. A bit in the
SYSERR register will also note when a fallback has occurred.
3
FF is used as a test of the fallback, but can also be used as a software-initiated fallback.
FF = 0,
Normal operation
FF = 1,
Force use of secondary (fallback) resources
2—0 The FCSEL choices are a subset of the CKSEL values from the CKM register above. The list is
presented below:
FCSEL = 000,
Internal oscillator divided by 4
FCSEL = 001,
Internal oscillator
FCSEL = 010,
A clocks (C8A & FRAMEA); ECTF or MC-1
FCSEL = 011,
B clocks (C8B & FRAMEB); ECTF or MC-1
FCSEL = 100,
NETREF
FCSEL = 101—111,
Selects local references 1—3
FTS
FF
FCSEL
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