參數(shù)資料
型號： T8100
英文描述： H.100/H.110 Interface and Time-Slot Interchanger
中文描述： H.100/H.110接口和時隙交換器
文件頁數(shù)： 33/92頁
文件大?。?/td> 1450K
代理商： T8100
Lucent Technologies Inc.
31
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Descrip-
tion
(continued)
2.3 H-Bus Section
(continued)
2.3.2 CAM Operation and Commands
The three CAMs operate in parallel. Each CAM’s com-
parand field is compared with the state counter (Sec-
tion 2.2.5 State Counter Operation) which holds the
existing stream and time-slot value*. If there is a match,
the CAM issues a hit. If there is more than one match,
then it is considered a multiple hit. Likewise, no match
is a miss. As a part of the state counter, a bit is toggled
for read/write. The read/write bit is stored in the CAM,
so it becomes part of the value to be compared. If the
comparison for a write yields a hit, then there is a
request for write access to the data memory for the
incoming data from the H-Bus. If the comparison for a
read yields a hit, then there is a request for a read
access from the data memory for outgoing data to the
H-Bus. Any multiple hit within one CAM block is treated
as a controlled error although it is not reported. The
action taken is to acknowledge the hit which corre-
sponds to the lowest physical address of the CAM. A
miss implies no action. A multiple hit is assigned to be
more than one valid connection. These are prioritized
such that the match with the lowest physical address
(i.e., closest to CAM location 0x0) is the address which
is processed. Thus, errors are handled in a controlled
manner. Multiple hits can occur because multiple loca-
tions are assigned to the same time slot. Bad software
can cause this problem. A controlled error has no
impact on performance, and the CAM contents are not
changed as a result of the error. The data SRAMs are
actually dual-port register files which will process both
writes and reads on each clock cycle of the clock. The
T8100 can process a read and write request from each
CAM and two microprocessor requests during the time
of one address comparison. Due to the fixed order of
operations, the data SRAM cannot overflow or under-
flow like the CAMs. The timing is shown in Figure 10.
* As mentioned in Section 2.2.5 State Counter Operation, for each
stream and time-slot value, the state counter goes through four
functional states for each stream and time slot. These states are
used to synchronize the CAMs, pipeline register files, data SRAMs,
and microprocessor accesses just as they are used to synchronize
local memory operations and the frame groups. (Microprocessor
accesses to the memories are initiated asynchronously, though the
actual microprocessor cycles are synchronous.)
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