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| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時隙交換器 |
| 文件頁數(shù)： | 49/92頁 |
| 文件大?。?/td> | 1450K |
| 代理商： | T8100 |
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Lucent Technologies Inc.
47
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Descrip-
tion
(continued)
2.5 Interface Section
(continued)
2.5.2 General-Purpose Register
A simple, general-purpose I/O register is available. The
GPR has eight dedicated pins to the T8100. A write to
the register forces it to operate as an output. It remains
as an output until a read from the register is performed
(which 3-states the output). The register powers up in
the input state with a cleared register. The GPR corre-
sponds with I/O pins GP[0:7]. GP6 and GP7 are
unavailable if bit 5 of register CKN is low (see Section
2.4.6 Clock Control Register Definitions).
2.5.3 Framing Groups
Two groups of frame pulses are available. Each frame
group consists of 12 lines which are enabled sequen-
tially after a programmed starting point. They are
denoted as group A and group B. This section
describes framing group A. Framing group B is made
up of similar registers. Each frame group is controlled
by a pair of registers: FRHA and FRLA control the
spacing of the 12 frame pulses, their pulse width,
polarity, and the offset of the first pulse from the frame
boundary.
Table 45. FRHA, Frame Group A High Address and Control, 0x21
Table 46. FRHB, Frame Group B High Address and Control, 0x23
REG
FRHA
R/W
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
FAI
Bit 2
Bit 1
Hi Start
Bit 0
Rate
Type
Symbol
Rate
Bit
7—6
Name/Description
Rate
Rate
Rate
Rate
Type
Type
Type
Type
FAI
FAI
Hi Start =
=
=
=
=
=
=
=
=
=
=
00,
01,
10,
11,
00,
01,
10,
11,
0,
1,
Upper 3 bits of group start address or programmed output
Frame group disabled, 3-state
2.048 Mbits/s
4.096 Mbits/s
8.192 Mbits/s
Bit-wide pulse
Double bit-wide pulse
Byte-wide pulse
Double byte-wide pulse
Normal pulse
Inverted pulse
Type
5—4
FAI
3
Hi Start
2—0
REG
FRHB
R/W
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
FAI
Bit 2
Bit 1
Hi Start
Bit 0
Rate
Type
Symbol
Rate
Bit
7—6
Name/Description
Rate
Rate
Rate
Rate
Type
Type
Type
Type
FAI
FAI
Hi Start =
=
=
=
=
=
=
=
=
=
=
00,
01,
10,
11,
00,
01,
10,
11,
0,
1,
Upper 3 bits of group start address
Frame group disabled, 3-state
2.048 Mbits/s
4.096 Mbits/s
8.192 Mbits/s
Bit-wide pulse
Double bit-wide pulse
Byte-wide pulse
Double byte-wide pulse
Normal pulse
Inverted pulse
Type
5—4
FAI
3
Hi Start
2—0
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