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參數(shù)資料
| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時隙交換器 |
| 文件頁數(shù)： | 56/92頁 |
| 文件大?。?/td> | 1450K |
| 代理商： | T8100 |
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54
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Descrip-
tion
(continued)
2.8 Testing and Diagnostics
(continued)
2.8.2 Diagnostics
(continued)
The three registers are presented in order below:
The register fields are interpreted as follows:
DFA—Diagnostics, Frame Pin Selects, Group A:
DFn = 00, Normal operation
DFn = 01, State counter bits [10:0] routed to frame
group pins [10:0], pin 11 = L
DFn = 10, Even CAM hit routed to pin 11, pin 10 has
odd CAM hit, pins [9:0] have local data
memory address
DFn = 11, Pin 11 gets CUE error bit, pin 10 gets CUO
error bit, pin 9 gets CUL error bit, pin 8 gets
COE error bit, pins [5:0] get page pointers—
8 MHz read, 8 MHz write, 4 MHz read,
4 MHz write, 2 MHz read, and 2 MHz write
DFB—Diagnostics, Frame Pin Selects, Group B:
DFn = 00, Normal operation
DFn = 01, State counter bits [10:0] routed to frame
group pins [10:0], pin 11 = L
DFn = 10, CAM state register [1:0] indicating four sub-
states, routed to pins [11:10], and local con-
nection memory address routed to pins [9:0]
DFn = 11, Pin 11 gets local CAM hit flag, and pins
[10:0] get CAM state counter
DMF—Diagnostics, Memory, Fill Test Enable:
DMF = 0, Normal operation
DMF = 1, Fill all memories with the pattern selected
by DMP
DMP—Diagnostics, Memory, Fill Test Pattern
Select:
DMP = 00, Checkerboard 0—even locations get 0x55,
odd locations get 0xAA
DMP = 01, Checkerboard 1—even locations get 0xAA,
odd locations get 0x55
DMP = 10, Data locations equal address bits [7:0]
(CAMs are filled with their physical address)
DMP = 11, Data locations equal inverted address bits
[7:0]
DMD—Diagnostics, Memory, Done Indicator:
This is a status bit which indicates that the chosen
memory pattern has been written to all locations. Addi-
tional writes to the memory are disabled and reads are
enabled. This condition remains until the user clears
this bit.
DFC—Diagnostics, Frame Groups Cycle Test
Mode:
DFC = 0, Normal operation
DFC = 1, Cycle test mode enabled; forces the frame
groups to constantly cycle without waiting for
a frame signal to synchronize the start.
DSB—Diagnostics, State Counter, Break Carry
Bits:
DSB = 0, Normal operation
DSB = 1, Breaks the carry bits between the subsec-
tions of the state counter so that the state
counter is operating as three counters run-
ning in parallel. (This can be viewed on the
frame pins using the DFn = 01 selection
described above.) Status counter bits [0:3]
and [4:7] run as modulo-16 counters, and bits
[8:10] run as a modulo-8 counter.
DXF—Diagnostics, External Frame Input:
DXF = 0, Normal operation
DXF = 1, Forces /FR_COMP to act as a direct input
signal for T8100 framing. This effectively
bypasses the internally generated frame sig-
nal. The user is again cautioned since the
external frame can operate asynchronously
to the generated clocks if care is not taken.
DSE—Diagnostics, State Counter, Enable Parallel
Load:
DSE = 0, Normal operation
DSE = 1, Forces the state counter to load the value
held in DSH and DSL and continuously cycle
as a modulo-n counter where the n value is
determined by (DSH and DSL). With the DSE
pin high, the state counter is no longer syn-
chronized to the frame signal.
DSH—Diagnostics, State Counter, High Bits of Par-
allel Load:
DSH = State counter bits [10:8]
DSL—Diagnostics, State Counter, Low Bits of Par-
allel Load:
DSL = State counter bits [7:0]
DFA
DFB
DMF
DMP
DMD
DFC
DSB
DXF
(Res.)
DSE
DSH
DSL
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