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參數(shù)資料
| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時隙交換器 |
| 文件頁數(shù)： | 58/92頁 |
| 文件大?。?/td> | 1450K |
| 代理商： | T8100 |
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56
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
3 Using the T8100
(continued)
3.2 Basic Connections
(continued)
3.2.1 Physical Connections for H.110
Figure 16 shows the T8100 physical connections
required for use in an H.110 environment. There are
electrical differences between H.100 and H.110. For
H.110, external components are required to meet spec-
ifications. Figure 16 shows the T8100 NETREF termi-
nations and the required terminations for CT_C8A,
CT_FRAMEA, CT_C8B, and CT_FRAMEB. Each sig-
nal has a mechanism to short the 33
series resistor
and, in addition, a 10 k
pulldown resistor. The 50 k
internal pull-ups on the CT data bus are used for
H.100. For H.110, the DPUE pin should be tied low,
disabling these internal pull-ups. H.110 requires the CT
data bus to have pull-ups of 18 k
to 0.7 V. The control
leads of the FET switches would typically go to the
microprocessor.
3.2.2 H.100 Data Pin Series Termination
All data bus lines must have a 24
series
resistor, even if only data lines 16—31 are used
at 8.192 Mbits/s.
3.2.3 PC Board Considerations
There are no special requirements for the thermal balls
on the BGA package when designing a printed-circuit
board.
5-7142F
Figure 16. Physical Connections for H.110
18 k
V
PULL-UP
=
CT_NETREF
CT_FRAMEA
CT_FRAMEB
CT_C8B
CT_NETREFB
CT_NETREFA
SCLKX2
CTD[0:31]
RDY AND PLL
CONNECTIONS
AS IN H.100
CT_C8B
SCLK
CT_FRAMEB
CT_FRAMEA
SCLK
33
LUCENT T8100
CT_C8A
10 k
CTC8A_SRC
33
10 k
CTC8A_SRC
33
10 k
CTC8B_SRC
33
10 k
CTC8B_SRC
0
DEPOPULATE
CT_C8A
SCLKX2
0
DEPOPULATE
CTD[0:31]
24
DPUE
0.7 V
18 k
32
18 k
V
PULL-UP
=
24
24
CTR_NETB
CTR_NETA
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