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| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時(shí)隙交換器 |
| 文件頁數(shù)： | 53/92頁 |
| 文件大?。?/td> | 1450K |
| 代理商： | T8100 |
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Lucent Technologies Inc.
51
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
2 Architecture and Functional Description
(continued)
2.7 The JTAG Test Access Port
2.7.1 Overview of the JTAG Architecture
Tap
A 5-pin test access port, consisting of input pins TCK, TMS, TDI, TDO,
and TRST, provides the standard interface to the test logic. TRST is an
active-low signal that resets the circuit.
TAP Controller
The TAP controller implements the finite state machine which controls the
operation of the test logic as defined by the standard. The TMS input
value sampled on the rising edge of TCK controls the state transitions.
The state diagram underlying the TAP controller is shown below.
Instruction Register (JIR)
A 3-bit scannable JTAG instruction register that communicates data or
commands between the TAP and the T8100 during test or HDS opera-
tions.
Boundary-Scan Register (JBSR)
A 211-bit JTAG boundary-scan register containing one scannable register
cell for every I/O pin and every 3-state enable signal of the device, as
defined by the standard. JBSR can capture from parallel inputs or update
into parallel outputs for every cell in the scan path. JBSR may be config-
ured into three standard modes of operation (EXTEST, INTEST, and
SAMPLE) by scanning the proper instruction code into the instruction reg-
ister (JIR). An in-depth treatment of the boundary-scan register, its physi-
cal structure, and its different cell types is given in Table 51.
Bypass Register (JBPR)
A 1-bit long JTAG bypass register to bypass the boundary-scan path of
nontargeted devices in board environments as defined by the standard.
2.7.2 Overview of the JTAG Instructions
The JTAG block supports the public instructions as shown in the table below.
Table 50. T8100 JTAG Instruction Set
Instruction
Mnemonics
EXTEST
SAMPLE
Reserved
Reserved
Reserved
Reserved
Reserved
BYPASS
Instruction
Codes
000
001
010
011
100
101
110
111
Public/Private
Mode
Description
Public
Public
—
—
—
—
—
Public
—
—
—
—
—
—
—
Select B-S register in extest mode
Select B-S register in sample mode
—
—
—
—
—
Select BYPASS register
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