參數(shù)資料
型號: T8100
英文描述: H.100/H.110 Interface and Time-Slot Interchanger
中文描述: H.100/H.110接口和時隙交換器
文件頁數(shù): 85/92頁
文件大?。?/td> 1450K
代理商: T8100
Lucent Technologies Inc.
83
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
Appendix A. Application of Clock Modes
(continued)
5-6131aF(r3)
Figure 32. E1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF
Source = 2.048 MHz from Trunk
x16
x32
x8
x16
4 MHz
2 MHz
FRAME SYNC
DPLL
DINETREF
DIVIDE REGISTER
DIVMAIN
DIVIDE REGISTER
CLOCK
RESOURCE
SELECT
BY 4
GP6
GP7
RESOURCE
DIVIDE REGISTER
NETREF
INT/EXT
SELECT
BIT SLIDER
CONTROLS
BIT SLIDER
STATE
MACHINES
PLL #1
PLL #1 BYPASS
RATE SELECT
65.536 MHz
PLL #2
PLL #2 BYPASS
RATE SELECT
PRIREFOUT
4MHzIN
3MHzIN
TCLK
TCLK
ENABLE
STCI
BY 2
NET-
REF
SEL.
÷
BY 8
SELECT
FSEL.
/CT_FRAME_A
/CT_FRAME_B
/FR_COMP
SEL.
SEL.
IAND
STATE
L_REF0
CT_NCT_C8
C/C4
±
SCC2
SCLK2
XTALIN
TODJAT/GP6
FROMDJAT/GP7
L_SC CTL
FRAME
FRAME
SEC8K
FRAME
EN_B
C8
FRAME
C6
EN_A
NETREF
EN_NETREF
CT_NETREF
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B
COMPATIBILITY
16CLOCKS DIRECTI/CT16
±
C2
/C4
SCLK
SCLK2
/FR_COMP
L_SC0
SCSEL
4.096 MHz
FRAMERS
(FALLBACK PATH)
DPLL#2-2
16.384 MHz
8.192 MHz
4.096 MHz
2.048 MHz
8.192 MHz
8.192 MHz
4.096 MHz
2.048 MHz
4.096 MHz
2.048 MHz
2 MHz DJAT
DJAT BYPASS
(AND GP 6/7 ENABLE)
(1 OF 4
L_SC[1:3]
NOT SHOWN)
2.L_REF7
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