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| 型號： | T8100 |
| 英文描述： | H.100/H.110 Interface and Time-Slot Interchanger |
| 中文描述： | H.100/H.110接口和時隙交換器 |
| 文件頁數(shù)： | 6/92頁 |
| 文件大小： | 1450K |
| 代理商： | T8100 |
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4
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
H.100/H.110 Interface and Time-Slot Interchanger
Ambassador T8100
Table of Contents
(continued)
Tables
Table 1. Pin Descriptions: Clocking and Framing
Pins ..............................................................6
Table 2. Pin Descriptions:
Local Streams Pins ...........8
Table 3. Pin Descriptions: H-Bus Pins ........................8
Table 4. Pin Descriptions: Microprocessor Interface
Pins ..............................................................9
Table 5. Pin Descriptions:
JTAG Pins .......................9
Table 6. Pin Descriptions: Power Pins ......................9
Table 7. Pin Descriptions: Other Pins ......................10
Table 8. Addresses of Programming Registers ........14
Table 9. Master Control and Status Register ..........14
Table 10. Address Mode Register ............................15
Table 11. Control Register Memory Space ..............16
Table 12. CKM: Clocks, Main Clock Selection,
0x00 .........................................................17
Table 13. CKN: Clocks, NETREF Selections,
0x01 .........................................................17
Table 14. CKP: Clocks, Programmable Outputs,
0x02 .........................................................17
Table 15. CKR: Clocks, Resource Selection,
0x03 .........................................................17
Table 16. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ........................................17
Table 17. CK32: Clocks, Locals 3 and 2, 0x05 ........17
Table 18. CK10: Clocks, Locals 1 and 0, 0x06 ........17
Table 19. CKMD: Clocks, Main Divider; CKND:
Clocks, NETREF Divider; CKRD: Clocks,
Resource Divider, 0x07, 0x08, 0x09 ........18
Table 20. LBS: Local Stream Control, 0x0C ............18
Table 21. CON: Connection Delay Type, 0x0E .......18
Table 22. HSL: H-Bus Stream Control, Low
Byte, 0x10 ...............................................18
Table 23. HSH: H-Bus Stream Control, High
Byte, 0x11 ...............................................18
Table 24. GPR: General-Purpose I/O Register,
0x18 .........................................................18
Table 25. FRLA: Frame Group A, Start Address
Low, 0x20 ................................................19
Table 26. FRHA: Frame Group A, High Address
and Control, 0x21 ....................................19
Table 27. FRLB: Frame Group B, Start Address
Low, 0x22 ................................................19
Table 28. FRHB: Frame Group B, High Address
and Control, 0x23 ....................................19
Table 29. FRPL: Frame Group B, Programmed
Output, Low, 0x24 ...................................19
Table 30. FRPH: Frame Group B, Programmed
Output, High, 0x25 ..................................19
Table 31. CLKERR1: Clock Error Register, Error
Indicator, 0x28 .........................................20
Table 32. CLKERR2: Clock Error Register, Current
Status, 0x29 ............................................20
Table 33. SYSERR: System Error Register,
0x2A ........................................................20
Table 34. CKW: Clock Error/Watchdog Masking
Register, 0x2B .........................................20
Page
Tables
Page
Table 35. DIAG1: Diagnostics Register 1, 0x30 ..... 20
Table 36. DIAG2: Diagnostics Register 2, 0x31 ..... 20
Table 37. DIAG3: Diagnostics Register 3, 0x32 ..... 20
Table 38. LBS: Local Stream Control, 0x0C ........... 27
Table 39. CKM: Clocks, Main Clock Selection,
0x00 ......................................................... 41
Table 40. CKN: Clocks, NETREF Selections,
0x01 ......................................................... 42
Table 41. CKP: Clocks, Programmable Outputs,
0x02 ......................................................... 43
Table 42. CKR: Clocks, Resource Selection,
0x03 ......................................................... 44
Table 43. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ........................................ 45
Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1,
and 0, 0x05 and 0x06 .............................. 46
Table 45. FRHA, Frame Group A High Address
and Control, 0x21 ................................... 47
Table 46. FRHB, Frame Group B High Address
and Control, 0x23 .................................... 47
Table 47. FRPH: Frame Group B, Programmed
Output, High, 0x25 .................................. 48
Table 48. CLKERR1 and CLKERR2: Error Indicator
and Current Status, 0x28 and 0x29 ......... 50
Table 49. SYSERR: System Error Register,
0x2A ........................................................ 50
Table 50. T8100 JTAG Instruction Set ................... 51
Table 51. T8100 JTAG Scan Register .................... 52
Table 52. Time-Slot Bit Decoding ............................ 57
Table 53. IDR: Indirect Data Register, Local
Connections Only .................................... 58
Table 54. IDR: Indirect Data Register, H-Bus
Connections Only ................................... 59
Table 55. Crystal Oscillator ..................................... 67
Table 56. Alternative to Crystal Oscillator ............... 67
Table 57. Electrical Drive Specifications—CT_C8
and /CT_FRAME ..................................... 67
Table 58. dc Electrical Characteristics, All Other
Pins .......................................................... 68
Table 59. ac Electrical Characteristics, Timing,
H-Bus (H.100, Spec., Rev. 1.0) .............. 72
Table 60. ac Electrical Characteristics, Skew
Timing, H-Bus (H.100, Spec., Rev. 1.0) . 73
Table 61. Reset and Power On ............................... 73
Table 62. ac Electrical Characteristics, Local
Streams, and Frames .............................. 74
Table 63. Microprocessor Access Timing (See
Figure 24 through Figure 29.) ................. 77
Table 64. Clock Register Programming Profile for
the Four Previous Examples .................. 85
Table 65. Table of Special Cases (Exceptions) ....... 88
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