Lucent Technologies Inc.
11
Advance Data Sheet
December 2000
Phone-On-A-Chip
IP Solution DSP
T8301 Internet Protocol Telephone
4 DSP1600 Core
(continued)
INT0N is dedicated to the
ARM
DCC interrupts in the DSP’s mask ROM. INT1N is internally ORed with the DMA
interrupt. The DSP’s mask ROM for INT1 is dedicated to DMA servicing. It is recommended that INT1N float (inter-
nal pull up on pin).
4.7 Power Management
There are three different power management control mechanisms: the
power control register
(
POWERC
), the
stop pin (
STOPN
), and the
AWAIT
bit in the
ALF
register
. Refer to the DSP1627 data sheet for more information
concerning these registers and their usage.
4.8 External Memory Interface (EMI)
The T8301 external memory interface is used to access the non-DSP1627 core features provided in the T8301
integrated circuit. The external memory interface is also used to access off-chip resources such as the interproces-
sor communication memories contained in the IPT_ARM integrated circuit.
The T8301 external memory interface requires one wait-state to access on-chip resources and two wait-states to
access 15 ns or faster off-chip resources when operating at 80 MHz.
4.9 T8301 Memory Mapping
The T8301 contains various types of memory modules, all with varying characteristics, aside from their memory
map location. As a Harvard architecture, the device has two address/data buses; these are referred to as X and Y.
The X system is used for program instructions and data, and the Y system is typically for data and memory
mapped I/O. Memory is 16 bits wide.
The DSP1627 can vary the X bus memory map based on the logic levels on two signals:
EXM
and
LOWPR
. How-
ever, the T8301 has
EXM
tied low internally, reducing the possibilities to two. The two memory maps are the
DSP1627’s MAP1 and MAP3.
LOWPR
is software controllable. When using the DSP1627 software tools (with JCS
i.e., JTAG communications system) the tools will configure
LOWPR
automatically based upon the link time compile
options of the
.if
file. Map1 is the default map. The basic difference of the two maps is the type of memory at the
reset vector (0x0000). MAP1 has ROM at 0x0000, and MAP3 has RAM at 0x0000. The Y map is fixed.
The T8301 is a masked ROM-coded device and contains no flash memory. MAP 1 is typically used for production,
and Map 3 is typically used for code development. When used in conjunction to the T8302
ARM
embedded proces-
sor, the
ARM
will be required to pass all code and data to the DSP's ram at power up reset. A hardware/software
protocol must be instituted to allow the ARM to successfully load code into the DSP
Note:
All X memory references are MAP 3.
I
Internal ROM, IROM—32K x 16:
— Responds only to the X data bus, the X memory location is 0x4000—0xBFFF. This block will operate with zero
wait-states.
Table 3. DSP1627 INT0N and INT1N
Interrupt
INT1N
INT0N
Function
Interrupt Priority
4 (higher)
2
Interrupt from DMA block or external interrupt 1, active-low.
External interrupt input 0, active-low.