
24
Lucent Technologies Inc.
Phone-On-A-Chip
IP Solution DSP
T8301 Internet Protocol Telephone
Advance Data Sheet
December 2000
6 DMA Input/Output Channels
(continued)
Table 14. DMA Control Register dmac_reg
DMA Control Register (dmac_reg) Address (0x4010)
14
13
12
IENSPK
IENHND
IENAIN
6
5
SPKBSY
HNDBSY
AINBSY
Bit #
Name
Bit #
Name
15
11
10
9
8
RSVD
7
RSVD
RSVD
3
RSVD
IONSPK
2
SPKGO
IONHND
1
HNDGO
IONAIN
0
AINGO
4
Bit #
15
14
13
12
11
10
Name
RSVD
IENSPK
IENHND
IENAIN
RSVD
IONSPK
Description
Reserved.
Interrupt enable speaker output channel.
Interrupt enable handset output channel.
Interrupt enable analog input channel.
Reserved.
Interrupt on speaker DMA channel. Indicates a transfer has completed. A physical
interrupt to the DSP will only occur if the
IENSPK
bit is also set. The interrupt is
cleared by a read operation.
Interrupt on handset DMA channel. Indicates a transfer has completed. A physical
interrupt to the DSP will only occur if the
IENHND
bit is also set. The interrupt is
cleared by a read operation.
Interrupt on analog input DMA channel. Indicates a transfer has completed. A physi-
cal interrupt to the DSP will only occur if the
IENAIN
bit is also set. The interrupt is
cleared by a read operation.
Reserved.
Speaker DMA channel busy (read only).
Handset DMA channel busy (read only).
Analog input DMA channel busy (read only).
Reserved.
DMA start. Starts the DMA channel when set to 1, automatically reset to zero when a
count of zero is reached by the DMA transfer counter.
DMA start. Starts the DMA channel when set to 1, automatically reset to zero when a
count of zero is reached by the DMA transfer counter.
DMA start. Starts the DMA channel when set to 1, automatically reset to zero when a
count of zero is reached by the DMA transfer counter.
9
IONHND
8
IONAIN
7
6
5
4
3
2
RSVD
SPKBSY
HNDBSY
AINBSY
RSVD
SPKGO
1
HNDGO
0
AINGO
Table 15. DMA Starting Address Register setadr_reg
Set DMA Address Registers [AINsetadr_reg Address (0x4014)] [HNDsetadr_reg Address (0x4018)]
[SPKsetadr_reg Address (0x401C)]
Bit #
15:9
Name
RSVD
8:0
DMA_ADDRESS_SET_UP[8:0]
Table 16. DMA Transfer Count Register setcnt_reg
Set DMA Count Registers [AINsetcnt_reg Address (0x4015)] [HNDsetcnt_reg Address (0x4019)]
[SPKsetcnt_reg Address (0x401D)]
Bit #
15:9
Name
RSVD
8:0
DMA_COUNT_SET_UP[8:0]