30
Lucent Technologies Inc.
Phone-On-A-Chip
IP Solution DSP
T8301 Internet Protocol Telephone
Advance Data Sheet
December 2000
9 JTAG and Hardware Development System (HDS)
The JTAG block contains logic for implementing the JTAG/
IEEE
* P1149.1 standard. A four-signal test port provides
a mechanism for accessing the DSP1627 core from remote test equipment or a remote hardware development
system. The on-chip HDS performs instruction breakpointing and branch tracing at full speed. Using the JTAG port,
the breakpointing is set up and the trace history is read back.
9.1 TMODE Control for JCS/Boundary-Scan Operation
TMODEN0, TMODEN1, and TMODEN2 are inputs used to determine test mode operation. Of the eight possible
combinations, modes 6 and 7 are significant during the development and production phases.
9.1.1 Mode 7 Operation (TMODE = 7)
This is the production mode. Internal pull-up resistors (approximately 50 k
) will provide the logic level required.
The three pins can be left floating (no external resistors are required). In this mode, boundary-scan is active. The
CK8KHz (pin 67), the CK2MHz (pin 98), and the CKO (pin 99) are all dormant (high).
9.1.2 Mode 6 Operation (TMODE = 6)
The JCS tools (JTAG communications system) are used in this mode. TMODEN0 must be pulled low externally,
TMODEN1, and TMODEN2 can both be left floating to enter this mode. The CK8KHz (pin 67), the CK2MHz
(pin 98), and the CKO (pin 99) are active.
Should the user require access to any or all of the three clocks in production and still require boundary-scan capa-
bilities for production test, a strong (external) pull-down resistor would be required on TMODEN0 (1 k
). The pro-
duction test must be able to pull TMODEN0 high to allow access to the boundary-scan test. After the test is
complete, the pin would normally be low (TMODE 6) allowing the clocks to be active.
9.2 The Principle of Boundary-Scan Architecture
Each primary input signal and primary output signal is supplemented with a multipurpose memory element called a
boundary-scan cell. Cells on device primary inputs are referred to as input cells and cells on primary outputs are
referred to as output cells. Input and output is relative to the core logic of the device.
At any time, only one register can be connected from TDI to TDO, e.g., the instruction register (IR), BYPASS,
boundary-scan, IDENT, or even some appropriate register internal to the core logic; see Figure 7. The selected
register is identified by the decoded output of the instruction register. Certain instructions are mandatory, such as
EXTEST
(boundary-scan register selected), whereas others are optional, such as the IDCODE
instruction (IDENT
register selected).
*
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.