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參數(shù)資料
| 型號(hào)： | T8301 |
| 英文描述： | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| 中文描述： | T8301因特網(wǎng)協(xié)議電話熱線電話在一個(gè)芯片⑩DSP的IP解決方案 |
| 文件頁數(shù)： | 23/190頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | T8301 |
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Lucent Technologies Inc.
23
Advance Data Sheet
December 2000
T8301 Internet Protocol Telephone
Phone-On-A-Chip
IP Solution DSP
6 DMA Input/Output Channels
The discussions in this section pertain to circuitry that is outside of the dotted outline in Figure 3 on page 8.
There are three timed DMA transfer blocks, each of which transfers data to/from the audio codec block from/to a
512 x 16-bit SRAM. These SRAMs are two-port devices. One port is connected to the DSP1627 address and data
bus, and the other is accessed by the DMA controller. These memories transfer data to/from the audio codec block
or
AOUTA
,
AIN
, and
SOUT
. These DMA blocks are capable of transferring a 16-bit word to/from the device’s A/D or
D/A at the following rates, which are set up by programming the
audio codec clock control register
:
I
8 kHz
I
16 kHz
Each channel initiates a transfer between the audio codec block and its respective SRAM on the rising edge of the
selected transfer clock.
6.1 DMA Operation
The T8301 has three timed DMA transfer channels. The DSP sets up a DMA channel by writing a starting address
and a transfer count into the
setadr_reg
(see Table 15) and
setcnt_reg
(see
Table 16). The DSP then sets the
channel’s
GO
bit in the
dmac_reg
(see Table 14). When the DMA finishes its current transfer operation, indicated
by the
BSY
bit in the
dmac_reg
going low, the DMA will transfer the contents of the
setadr_reg
(see Table 15) to
the
adrinc_reg
(see Table 17) and the
cntdec_reg
(see Table 18) respectively. The
GO
bit will be reset to zero and
the
BSY
bit will be set to one, in the
dmac_reg
on completion of this transfer. When the rising edge of the transfer
clock is detected, the DMA controller will transfer a single word to/from memory and the audio codec block. The
DMA channel will then increment its address pointer
adrinc_reg
and decrement its counter
cntdec_reg
. At the
completion of the number of transfers written into the transfer counter (
cntdec_reg
= 0), the DMA block will set its
ION
bit in the
dmac_reg
to 1 and reset its
BSY
bit to zero. If its
IEN
bit is set, an interrupt to the DSP will occur. If
the DSP has set the
GO
bit which indicates that it has set up a new transfer or if the DSP responds (sets up a new
transfer count and re-enables transfers) before the next rising edge of the transfer clock, data can be continuously
transferred at the clocked rate.
If the DSP is reading or writing to the memory that a timed DMA is transferring to/from, the DMA can be delayed by
a clock cycle to allow the DSP to finish its access.
6.2 DMA Registers
Each DMA channel has the following four registers:
I
Starting address register
I
Transfer count register
I
Working address increment register (read only)
I
Working count decrement register (read only)
In addition, there is a control and status register that supports all three DMA channels.
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PDF描述 |
|---|---|
| T8302 | T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| T8502 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8503 | T8502 and T8503 Dual PCM Codecs with Filters |
| T8531A | T8531A/8532 Multichannel Programmable Codec Chip Set |
| T8531 | T8502 and T8503 Dual PCM Codecs with Filters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8301AX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8301BX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8301DX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| T8302A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
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