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參數(shù)資料
| 型號(hào)： | T8301 |
| 英文描述： | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| 中文描述： | T8301因特網(wǎng)協(xié)議電話熱線電話在一個(gè)芯片⑩DSP的IP解決方案 |
| 文件頁(yè)數(shù)： | 124/190頁(yè) |
| 文件大?。?/td> | 1535K |
| 代理商： | T8301 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
88
Lucent Technologies Inc.
10 Timing Characteristics for 5 V Operation
(continued)
Figure 24. PHIF MotorolaMode Signaling (Read and Write) Timing Diagram
*
This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For
example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after
PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN
should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
*
This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also
be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For
example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low after
PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to PCSN
should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.
PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to be
the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 88. Timing Requirements for PHIF MotorolaMode Signaling
Abbreviated Reference
t41
t42
Parameter
Min
0
0
Max
—
—
Unit
ns
ns
PDS
to PCSN Setup (valid to low)
PCSN to PDS
Hold (high to invalid)
PRWN to PCSN Setup (valid to low)
PCSN to PRWN Hold (high to invalid)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
4.5
0
4.5
0
4.5
0
8
4
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Table 89. Timing Characteristics for PHIF MotorolaMode Signaling
Abbreviated Reference
t49*
t50*
Parameter
Min
—
3
Max
13
—
Unit
ns
ns
PCSN to PB Read (low to valid)
PCSN to PB Read (high to invalid)
5-4038 (F).a
PCSN
PDS
PRWN
PBSEL
PSTAT
PB[7:0]
t41
t42
t43
t44
t45
t46
t47
t48
t52
t51
t50
t154
t49
16-bit READ
16-bit WRITE
t43
t44
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
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| T8301AX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8301BX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
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