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| 型號： | T8301 |
| 英文描述： | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| 中文描述： | T8301因特網(wǎng)協(xié)議電話熱線電話在一個芯片⑩DSP的IP解決方案 |
| 文件頁數(shù)： | 72/190頁 |
| 文件大小： | 1535K |
| 代理商： | T8301 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
36
Lucent Technologies Inc.
5 Software Architecture
5.1 Instruction Set
The DSP1627 processor has seven types of instruc-
tions: multiply/ALU, special function, control, F3 ALU,
BMU, cache, and data move. The multiply/ALU instruc-
tions are the primary instructions used to implement sig-
nal processing algorithms. Statements from this group
can be combined to generate multiply/accumulate, log-
ical, and other ALU functions and to transfer data be-
tween memory and registers in the data arithmetic unit.
The special function instructions can be conditionally
executed based on flags from the previous ALU or BMU
operation, the condition of one of the counters, or the
value of a pseudorandom bit in the DSP1627 device.
Special function instructions perform shift, round, and
complement functions. The F3 ALU instructions enrich
the operations available on accumulators. The BMU in-
structions provide high-performance bit manipulation.
The control instructions implement the goto and call
commands. Control instructions can also be executed
conditionally. Cache instructions are used to implement
low-overhead loops, conserve program memory, and
decrease the execution time of certain multiply/ALU in-
structions. Data move instructions are used to transfer
data between memory and registers or between accu-
mulators and registers. See the DSP1611/17/18/27
Digital Signal Processor Information Manual or a de-
tailed description of the instruction set.
The following operators are used in describing the in-
struction set:
I
*
16 x 16-bit –> 32-bit multiplication
or
register-in-
direct addressing when used as a prefix to an ad-
dress register
or
denotes direct addressing
when used as a prefix to an immediate
I
+
36-bit addition
I
–
36-bit subtraction
I
>>
Arithmetic right shift
I
>>>
Logical right shift
I
<<
Arithmetic left shift
I
<<<
Logical left shift
I
|
36-bit bitwise OR
I
&
36-bit bitwise AND
I
^
36-bit bitwise EXCLUSIVE OR
I
:
Compound address swapping, accumulator
shuffling
I
~
One's complement
These are 36-bit operations. One operand is 36-bit data in an ac-
cumulator; the other operand may be 16, 32, or 36 bits.
Multiply/ALU Instructions
Note that the function statements and transfer state-
ments in Table 13 are chosen independently. Any func-
tion statement (F1) can be combined with any transfer
statement to form a valid multiply/ALU instruction. If ei-
ther statement is not required, a single statement from
either column also constitutes a valid instruction. The
number of cycles to execute the instruction is a function
of the transfer column. (An instruction with no transfer
statement executes in one instruction cycle.) Whenever
PC, pt, or rM is used in the instruction and points to ex-
ternal memory, the programmed number of wait-states
must be added to the instruction cycle count. All multi-
ply/ALU instructions require one word of program mem-
ory. The no-operation (
nop
) instruction is a special-
case encoding of a multiply/ALU instruction and exe-
cutes in one cycle. The assembly-language representa-
tion of a
nop
is either
nop
or a single semicolon.
A single-cycle squaring function is provided in
DSP1627. By setting the X = Y = bit in the auc register,
any instruction that loads the high half of the y register
also loads the x register with the same value. A subse-
quent instruction to multiply the x register and y register
results in the square of the value being placed in the p
register. The instruction a0 = p p = x*y y = *r0++ with
the X = Y = bit set to one will read the value pointed to
by r0, load it to both x and y, multiply the previously
fetched value of x and y, and transfer the previous prod-
uct to a0. A table of values pointed to by r0 can thus be
squared in a pipeline with one instruction cycle per each
value. Multiply/ALU instructions that use x = X transfer
statements (such as a0 = p p = x*y y = *r0++ x = *pt++)
are not recommended for squaring because pt will be
incremented even though x is not loaded from the value
pointed to by pt. Also, the same conflict wait occurrenc-
es from reading the same bank of internal memory or
reading from external memory apply, since the X space
fetch occurs (even though its value is not used).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T8301AX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8301BX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8301DX | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
| T8302 | 制造商:AGERE 制造商全稱:AGERE 功能描述:T8302 Internet Protocol Telephone Advanced RISC Machine (ARM) Ethernet QoS Using IEEE 802.1q |
| T8302A | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Terminator Die |
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