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| 型號(hào)： | T8301 |
| 英文描述： | T8301 Internet Protocol Telephone Phone-On-A-Chip⑩ IP Solution DSP |
| 中文描述： | T8301因特網(wǎng)協(xié)議電話熱線電話在一個(gè)芯片⑩DSP的IP解決方案 |
| 文件頁數(shù)： | 122/190頁 |
| 文件大小： | 1535K |
| 代理商： | T8301 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
86
Lucent Technologies Inc.
10 Timing Characteristics for 5 V Operation
(continued)
10.8 PHIF Specifications
For the PHIF, "READ" means read by the external user (output by the DSP); "WRITE" is similarly defined. The 8-bit reads/
writes are identical to one-half of a 16-bit access.
Figure 22. PHIF Intel Mode Signaling (Read and Write) Timing Diagram
*
This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also be initiated
and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever comes last. For example,
the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS goes low after PCSN. An output
transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated by PCSN or PIDS going low, whichever
comes last. An input transaction is completed by PCSN or PIDS going high, whichever comes first. All requirements referenced to PCSN apply to PIDS or
PODS, if PIDS or PODS is the controlling signal.
*
This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also be initiated
and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever comes last. For example,
the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS goes low after PCSN. An output
transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated by PCSN or PIDS going low, whichever
comes last. An input transaction is completed by PCSN or PIDS going high, whichever comes first. All requirements referenced to PCSN apply to PIDS or
PODS, if PIDS or PODS is the controlling signal.
Table 84. Timing Requirements for PHIF Intel Mode Signaling
Abbreviated Reference
t41
t42
t43
t44
t45*
t46*
t47*
t48*
t51*
t52*
Parameter
Min
0
0
0
0
4.5
0
4.5
0
7.5
4
Max
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PODS to PCSN Setup (low to low)
PCSN to PODS Hold (high to high)
PIDS to PCSN Setup (low to low)
PCSN to PIDS Hold (high to high)
PSTAT to PCSN Setup (valid to low)
PCSN to PSTAT Hold (high to invalid)
PBSEL to PCSN Setup (valid to low)
PCSN to PBSEL Hold (high to invalid)
PB Write to PCSN Setup (valid to high)
PCSN to PB Write Hold (high to invalid)
Table 85. Timing Characteristics for PHIF Intel Mode Signaling
Abbreviated Reference
t49*
t50*
Parameter
Min
—
3
Max
13
—
Unit
ns
ns
PCSN to PB Read (low to valid)
PCSN to PB Read Hold (high to invalid)
PCSN
t41
t42
t43
t45
t46
t49
t50
t154
16-bit READ
16-bit WRITE
PODS
PIDS
PBSEL
PSTAT
PB[7:0]
t47
t51
t52
t48
t44
5-4036 (F)
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
V
IH
–
V
IL
–
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