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| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設(shè)裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設(shè)裝置帶SBU的主機接口設(shè)備） |
| 文件頁數(shù)： | 27/49頁 |
| 文件大小： | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
null-AAL processing
Null-AAL processing uses the same mechanism as AAL3/4 in the transmit direction to disable AAL5 processing.
The control entry associated with each BWG (VCI) in the receive direction has an entry to indicate an interval
defined in units of cells received. The PCI SAR then provides an interrupt to the host when the number of cells
received on the VCI is equal to that indicated by the table entry. This counter is reset after each interrupt (at the
end of each interval). This interval is also referred to as a packet, although it does not encapsulate a well-defined
unit of information.
OAM processing
ATM-layer OAM processing does not require real-time intervention and is processed in software. OAM cells
received on the link are identified by the PCI SAR.
high-order VPI/VCI bits and GFC processing
The lower ten bits of the VCI are used to encode the 1023 possible VCIs. VCI 0 is not used since it indicates
unassigned cells. The upper-order bits of the VCI and the VPI field are programmable on a per-VC basis on
transmit. The generic-flow-control (GFC) field is always set to zero.
The upper-order bits of the VCI, the VPI field, and the GFC field are ignored on all cells that are received. These
cells are only passed to the PCI SAR if the header-error-control (HEC) field is correct, the upper-order bits of
the header are set intentionally, or the cell is misrouted. The probability of misrouting is small and such an event
would be detected via the CRC check in AAL5. The advantage of this scheme is that any VPI/VCI combination
is supported if the lower ten bits of the VCI are unique.
ATM-layer OAM encoding
NO.
ITEM
VCI
PTI
1
VP level: link-associated OAM cell
3
–
2
VP level: end-to-end OAM cell
4
–
3
VC level: link-associated OAM cell
Any
4
4
VC level: end-to-end OAM cell
Any
5
Each OAM cell forms a fully encapsulated packet. ATM-layer OAM cells transcend AAL protocols and are
recognized differently. The end system recognizes all four ATM-layer OAM flows. OAM cells received on
VCI 3 and 4 do not interfere with the normal data stream. The only special processing necessary is to initiate
EOP processing for each cell. The software driver must configure VCI 3 and 4 as null-AAL channels with a
packet length equal to one cell in the receive direction. OAM cells are transmitted as null-AAL packets with
length equal to one cell. VC-level OAM cells are specially interpreted. They are diverted to receive DMA channel
0 and the 4-byte ATM header is passed on to a receive completion ring in host memory during normal EOP
processing.
transmit descriptor rings and DMA
Each transmit BWG is supported by a corresponding DMA channel and its own descriptor ring. The PCI SAR
supports 255 BWGs, 255 descriptor rings, and 255 DMA channels in the transmit direction. This implies that
the number of packets and VCs that are active simultaneously is limited to 255. BWG 0 represents null and a
null cell is transmitted. This null cell is generated by the PCI SAR and no data is buffered in the FIFO memory
for transmission.
Each descriptor ring holds up to 256 entries corresponding to 256 buffers that can be queued for transmission
for that ring. The total number of buffers that can be queued for transmission is approximately 64K (256 buffers
per descriptor ring x 255 descriptor rings). The buffers within a descriptor ring are serviced in FIFO order on a
per-buffer basis.
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